Add bootph-pre-ram property for all the nodes used in SPL stage,
for syncing it later to u-boot j784s4 dts.
This series will be ported to the u-boot k3-j784s4 support patch series,
and was requested in its review process:
https://lore.kernel.org/u-boot/20230321155227.GV8135@bill-the-cat/
Changelog:
1) Added k3-am69-sk.dts bootph-pre-ram patch
2) Added bootph-pre-ram for wkup_pmx0 and ospi0
3) Added bootph-pre-ram for mcu_timer1
Link to v1: https://lore.kernel.org/linux-arm-kernel/[email protected]/
Apurva Nandan (4):
arm64: dts: ti: k3-j784s4-main: Add bootph-pre-ram property for SPL
nodes
arm64: dts: ti: k3-j784s4-mcu-wakeup: Add bootph-pre-ram property for
SPL nodes
arm64: dts: ti: k3-j784s4-evm: Add bootph-pre-ram property for SPL
nodes
arm64: dts: ti: k3-am69-sk: Add bootph-pre-ram property for SPL nodes
arch/arm64/boot/dts/ti/k3-am69-sk.dts | 13 ++++++++++
arch/arm64/boot/dts/ti/k3-j784s4-evm.dts | 25 +++++++++++++++++++
arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 3 +++
.../boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi | 10 ++++++++
4 files changed, 51 insertions(+)
--
2.34.1
Add bootph-pre-ram property for all the nodes used in SPL stage,
for syncing it later to u-boot k3-am69 dts.
Signed-off-by: Apurva Nandan <[email protected]>
---
arch/arm64/boot/dts/ti/k3-am69-sk.dts | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-am69-sk.dts b/arch/arm64/boot/dts/ti/k3-am69-sk.dts
index d282c2c633c1..cbe88a26b283 100644
--- a/arch/arm64/boot/dts/ti/k3-am69-sk.dts
+++ b/arch/arm64/boot/dts/ti/k3-am69-sk.dts
@@ -110,7 +110,9 @@ vdd_sd_dv: regulator-tlv71033 {
};
&main_pmx0 {
+ bootph-pre-ram;
main_uart8_pins_default: main-uart8-default-pins {
+ bootph-pre-ram;
pinctrl-single,pins = <
J784S4_IOPAD(0x0d0, PIN_INPUT, 11) /* (AP38) SPI0_CS1.UART8_RXD */
J784S4_IOPAD(0x0d4, PIN_OUTPUT, 11) /* (AN38) SPI0_CLK.UART8_TXD */
@@ -125,6 +127,7 @@ J784S4_IOPAD(0x0e4, PIN_INPUT_PULLUP, 0) /* (AP37) I2C0_SDA */
};
main_mmc1_pins_default: main-mmc1-default-pins {
+ bootph-pre-ram;
pinctrl-single,pins = <
J784S4_IOPAD(0x104, PIN_INPUT, 0) /* (AB38) MMC1_CLK */
J784S4_IOPAD(0x108, PIN_INPUT, 0) /* (AB36) MMC1_CMD */
@@ -164,7 +167,9 @@ J784S4_IOPAD(0x004, PIN_INPUT, 7) /* (AG36) MCAN12_TX.GPIO0_1 */
};
&wkup_pmx2 {
+ bootph-pre-ram;
wkup_uart0_pins_default: wkup-uart0-default-pins {
+ bootph-pre-ram;
pinctrl-single,pins = <
J721S2_WKUP_IOPAD(0x070, PIN_INPUT, 0) /* (L37) WKUP_GPIO0_6.WKUP_UART0_CTSn */
J721S2_WKUP_IOPAD(0x074, PIN_INPUT, 0) /* (L36) WKUP_GPIO0_7.WKUP_UART0_RTSn */
@@ -174,6 +179,7 @@ J721S2_WKUP_IOPAD(0x04c, PIN_INPUT, 0) /* (K34) WKUP_UART0_TXD */
};
wkup_i2c0_pins_default: wkup-i2c0-default-pins {
+ bootph-pre-ram;
pinctrl-single,pins = <
J721S2_WKUP_IOPAD(0x98, PIN_INPUT, 0) /* (N33) WKUP_I2C0_SCL */
J721S2_WKUP_IOPAD(0x9c, PIN_INPUT, 0) /* (N35) WKUP_I2C0_SDA */
@@ -181,6 +187,7 @@ J721S2_WKUP_IOPAD(0x9c, PIN_INPUT, 0) /* (N35) WKUP_I2C0_SDA */
};
mcu_uart0_pins_default: mcu-uart0-default-pins {
+ bootph-pre-ram;
pinctrl-single,pins = <
J784S4_WKUP_IOPAD(0x08c, PIN_INPUT, 0) /* (K38) WKUP_GPIO0_13.MCU_UART0_RXD */
J784S4_WKUP_IOPAD(0x088, PIN_OUTPUT, 0) /* (J37) WKUP_GPIO0_12.MCU_UART0_TXD */
@@ -242,6 +249,7 @@ J784S4_WKUP_IOPAD(0x0, PIN_INPUT, 7) /* (M33) WKUP_GPIO0_49 */
};
&wkup_uart0 {
+ bootph-pre-ram;
/* Firmware usage */
status = "reserved";
pinctrl-names = "default";
@@ -249,6 +257,7 @@ &wkup_uart0 {
};
&wkup_i2c0 {
+ bootph-pre-ram;
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&wkup_i2c0_pins_default>;
@@ -268,6 +277,7 @@ &wkup_gpio0 {
};
&mcu_uart0 {
+ bootph-pre-ram;
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&mcu_uart0_pins_default>;
@@ -281,6 +291,7 @@ &mcu_i2c0 {
};
&main_uart8 {
+ bootph-pre-ram;
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_uart8_pins_default>;
@@ -307,6 +318,7 @@ exp1: gpio@21 {
};
&main_sdhci0 {
+ bootph-pre-ram;
/* eMMC */
status = "okay";
non-removable;
@@ -315,6 +327,7 @@ &main_sdhci0 {
};
&main_sdhci1 {
+ bootph-pre-ram;
/* SD card */
status = "okay";
pinctrl-0 = <&main_mmc1_pins_default>;
--
2.34.1