Add legacy 32bit i.MX PCIe EP mode support
The PCI controller contained in i.MX6/7 legacy SOCs is one dual mode
PCIe controller, and can work either as RC or EP.
This series add i.MX6/7 PCIe EP mode supports. And had been verified
on i.MX6 sabresd and i.MX7 SDB boards.
In the verification, one board PCIe is used as RC, the other one is used
as EP.
Use the cross TX/RX differential cable connect the two PCIe ports of
these two boards.
+-----------+ +------------+
| PCIe TX |<-------------->|PCIe RX |
| | | |
| Board | | Board |
| | | |
| PCIe RX |<-------------->|PCIe TX |
+-----------+ +------------+
Changes from v2 to v3:
Add Reviewed-by: Krzysztof Kozlowski <[email protected]>
into dt-bindings patches.
Changes from v1 to v2:
Refer to Frank's comments:
To simple .get_features codes, add "const struct pci_epc_features"
*epc_features in drvdata.
Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-ep.yaml | 50 +++++++++++++++++++++++++++++++++++++++++----
arch/arm/boot/dts/nxp/imx/imx6qdl.dtsi | 14 +++++++++++++
arch/arm/boot/dts/nxp/imx/imx6qp.dtsi | 4 ++++
arch/arm/boot/dts/nxp/imx/imx6sx.dtsi | 17 +++++++++++++++
arch/arm/boot/dts/nxp/imx/imx7d.dtsi | 27 ++++++++++++++++++++++++
drivers/pci/controller/dwc/pci-imx6.c | 93 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
6 files changed, 201 insertions(+), 4 deletions(-)
[PATCH v3 1/9] dt-bindings: PCI: fsl,imx6q: Add i.MX6Q and i.MX6QP
[PATCH v3 2/9] dt-bindings: PCI: fsl,imx6q: Add i.MX6SX PCIe EP
[PATCH v3 3/9] dt-bindings: PCI: fsl,imx6q: Add i.MX7D PCIe EP
[PATCH v3 4/9] arm: dts: nxp: Add i.MX6QDL and i.MX6QP PCIe EP
[PATCH v3 5/9] arm: dts: nxp: Add i.MX6SX PCIe EP support
[PATCH v3 6/9] arm: dts: nxp: Add i.MX7D PCIe EP support
[PATCH v3 7/9] PCI: imx6: Add i.MX6Q and i.MX6QP PCIe EP supports
[PATCH v3 8/9] PCI: imx6: Add i.MX6SX PCIe EP support
[PATCH v3 9/9] PCI: imx6: Add i.MX7D PCIe EP support
Add the i.MX7D PCIe EP mode support.
Signed-off-by: Richard Zhu <[email protected]>
---
drivers/pci/controller/dwc/pci-imx6.c | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c
index 43c5251f5160..af7659712537 100644
--- a/drivers/pci/controller/dwc/pci-imx6.c
+++ b/drivers/pci/controller/dwc/pci-imx6.c
@@ -52,6 +52,7 @@ enum imx6_pcie_variants {
IMX6QP,
IMX6QP_EP,
IMX7D,
+ IMX7D_EP,
IMX8MQ,
IMX8MM,
IMX8MP,
@@ -359,6 +360,7 @@ static void imx6_pcie_init_phy(struct imx6_pcie *imx6_pcie)
0);
break;
case IMX7D:
+ case IMX7D_EP:
regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
IMX7D_GPR12_PCIE_PHY_REFCLK_SEL, 0);
break;
@@ -590,6 +592,7 @@ static int imx6_pcie_enable_ref_clk(struct imx6_pcie *imx6_pcie)
IMX6Q_GPR1_PCIE_REF_CLK_EN, 1 << 16);
break;
case IMX7D:
+ case IMX7D_EP:
break;
case IMX8MM:
case IMX8MM_EP:
@@ -638,6 +641,7 @@ static void imx6_pcie_disable_ref_clk(struct imx6_pcie *imx6_pcie)
IMX6Q_GPR1_PCIE_TEST_PD);
break;
case IMX7D:
+ case IMX7D_EP:
regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
IMX7D_GPR12_PCIE_PHY_REFCLK_SEL,
IMX7D_GPR12_PCIE_PHY_REFCLK_SEL);
@@ -711,6 +715,7 @@ static void imx6_pcie_assert_core_reset(struct imx6_pcie *imx6_pcie)
{
switch (imx6_pcie->drvdata->variant) {
case IMX7D:
+ case IMX7D_EP:
case IMX8MQ:
case IMX8MQ_EP:
reset_control_assert(imx6_pcie->pciephy_reset);
@@ -763,6 +768,7 @@ static int imx6_pcie_deassert_core_reset(struct imx6_pcie *imx6_pcie)
reset_control_deassert(imx6_pcie->pciephy_reset);
break;
case IMX7D:
+ case IMX7D_EP:
reset_control_deassert(imx6_pcie->pciephy_reset);
/* Workaround for ERR010728, failure of PCI-e PLL VCO to
@@ -854,6 +860,7 @@ static void imx6_pcie_ltssm_enable(struct device *dev)
IMX6Q_GPR12_PCIE_CTL_2);
break;
case IMX7D:
+ case IMX7D_EP:
case IMX8MQ:
case IMX8MQ_EP:
case IMX8MM:
@@ -880,6 +887,7 @@ static void imx6_pcie_ltssm_disable(struct device *dev)
IMX6Q_GPR12_PCIE_CTL_2, 0);
break;
case IMX7D:
+ case IMX7D_EP:
case IMX8MQ:
case IMX8MQ_EP:
case IMX8MM:
@@ -1385,6 +1393,7 @@ static int imx6_pcie_probe(struct platform_device *pdev)
"pcie_aux clock source missing or invalid\n");
fallthrough;
case IMX7D:
+ case IMX7D_EP:
if (dbi_base->start == IMX8MQ_PCIE2_BASE_ADDR)
imx6_pcie->controller_id = 1;
@@ -1572,6 +1581,12 @@ static const struct imx6_pcie_drvdata drvdata[] = {
.flags = IMX6_PCIE_FLAG_SUPPORTS_SUSPEND,
.gpr = "fsl,imx7d-iomuxc-gpr",
},
+ [IMX7D_EP] = {
+ .variant = IMX7D_EP,
+ .mode = DW_PCIE_EP_TYPE,
+ .gpr = "fsl,imx7d-iomuxc-gpr",
+ .epc_features = &imx6q_pcie_epc_features,
+ },
[IMX8MQ] = {
.variant = IMX8MQ,
.gpr = "fsl,imx8mq-iomuxc-gpr",
@@ -1611,6 +1626,7 @@ static const struct of_device_id imx6_pcie_of_match[] = {
{ .compatible = "fsl,imx6qp-pcie", .data = &drvdata[IMX6QP], },
{ .compatible = "fsl,imx6qp-pcie-ep", .data = &drvdata[IMX6QP_EP], },
{ .compatible = "fsl,imx7d-pcie", .data = &drvdata[IMX7D], },
+ { .compatible = "fsl,imx7d-pcie-ep", .data = &drvdata[IMX7D_EP], },
{ .compatible = "fsl,imx8mq-pcie", .data = &drvdata[IMX8MQ], },
{ .compatible = "fsl,imx8mm-pcie", .data = &drvdata[IMX8MM], },
{ .compatible = "fsl,imx8mp-pcie", .data = &drvdata[IMX8MP], },
--
2.34.1
Add i.MX6SX PCIe EP support.
Signed-off-by: Richard Zhu <[email protected]>
---
arch/arm/boot/dts/nxp/imx/imx6sx.dtsi | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
diff --git a/arch/arm/boot/dts/nxp/imx/imx6sx.dtsi b/arch/arm/boot/dts/nxp/imx/imx6sx.dtsi
index f6b35923ad83..13411a843e07 100644
--- a/arch/arm/boot/dts/nxp/imx/imx6sx.dtsi
+++ b/arch/arm/boot/dts/nxp/imx/imx6sx.dtsi
@@ -1471,5 +1471,22 @@ pcie: pcie@8ffc000 {
power-domain-names = "pcie", "pcie_phy";
status = "disabled";
};
+
+ pcie_ep: pcie-ep@8ffc000 {
+ compatible = "fsl,imx6sx-pcie-ep";
+ reg = <0x08ffc000 0x04000>, <0x08000000 0xf00000>;
+ reg-names = "dbi", "addr_space";
+ num-lanes = <1>;
+ clocks = <&clks IMX6SX_CLK_PCIE_AXI>,
+ <&clks IMX6SX_CLK_LVDS1_OUT>,
+ <&clks IMX6SX_CLK_PCIE_REF_125M>,
+ <&clks IMX6SX_CLK_DISPLAY_AXI>;
+ clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_inbound_axi";
+ power-domains = <&pd_disp>, <&pd_pci>;
+ power-domain-names = "pcie", "pcie_phy";
+ num-ib-windows = <4>;
+ num-ob-windows = <4>;
+ status = "disabled";
+ };
};
};
--
2.34.1
On Tue, Aug 08, 2023 at 01:34:18PM +0800, Richard Zhu wrote:
> Add the i.MX7D PCIe EP mode support.
>
> Signed-off-by: Richard Zhu <[email protected]>
Acked-by: Manivannan Sadhasivam <[email protected]>
- Mani
> ---
> drivers/pci/controller/dwc/pci-imx6.c | 16 ++++++++++++++++
> 1 file changed, 16 insertions(+)
>
> diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c
> index 43c5251f5160..af7659712537 100644
> --- a/drivers/pci/controller/dwc/pci-imx6.c
> +++ b/drivers/pci/controller/dwc/pci-imx6.c
> @@ -52,6 +52,7 @@ enum imx6_pcie_variants {
> IMX6QP,
> IMX6QP_EP,
> IMX7D,
> + IMX7D_EP,
> IMX8MQ,
> IMX8MM,
> IMX8MP,
> @@ -359,6 +360,7 @@ static void imx6_pcie_init_phy(struct imx6_pcie *imx6_pcie)
> 0);
> break;
> case IMX7D:
> + case IMX7D_EP:
> regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
> IMX7D_GPR12_PCIE_PHY_REFCLK_SEL, 0);
> break;
> @@ -590,6 +592,7 @@ static int imx6_pcie_enable_ref_clk(struct imx6_pcie *imx6_pcie)
> IMX6Q_GPR1_PCIE_REF_CLK_EN, 1 << 16);
> break;
> case IMX7D:
> + case IMX7D_EP:
> break;
> case IMX8MM:
> case IMX8MM_EP:
> @@ -638,6 +641,7 @@ static void imx6_pcie_disable_ref_clk(struct imx6_pcie *imx6_pcie)
> IMX6Q_GPR1_PCIE_TEST_PD);
> break;
> case IMX7D:
> + case IMX7D_EP:
> regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
> IMX7D_GPR12_PCIE_PHY_REFCLK_SEL,
> IMX7D_GPR12_PCIE_PHY_REFCLK_SEL);
> @@ -711,6 +715,7 @@ static void imx6_pcie_assert_core_reset(struct imx6_pcie *imx6_pcie)
> {
> switch (imx6_pcie->drvdata->variant) {
> case IMX7D:
> + case IMX7D_EP:
> case IMX8MQ:
> case IMX8MQ_EP:
> reset_control_assert(imx6_pcie->pciephy_reset);
> @@ -763,6 +768,7 @@ static int imx6_pcie_deassert_core_reset(struct imx6_pcie *imx6_pcie)
> reset_control_deassert(imx6_pcie->pciephy_reset);
> break;
> case IMX7D:
> + case IMX7D_EP:
> reset_control_deassert(imx6_pcie->pciephy_reset);
>
> /* Workaround for ERR010728, failure of PCI-e PLL VCO to
> @@ -854,6 +860,7 @@ static void imx6_pcie_ltssm_enable(struct device *dev)
> IMX6Q_GPR12_PCIE_CTL_2);
> break;
> case IMX7D:
> + case IMX7D_EP:
> case IMX8MQ:
> case IMX8MQ_EP:
> case IMX8MM:
> @@ -880,6 +887,7 @@ static void imx6_pcie_ltssm_disable(struct device *dev)
> IMX6Q_GPR12_PCIE_CTL_2, 0);
> break;
> case IMX7D:
> + case IMX7D_EP:
> case IMX8MQ:
> case IMX8MQ_EP:
> case IMX8MM:
> @@ -1385,6 +1393,7 @@ static int imx6_pcie_probe(struct platform_device *pdev)
> "pcie_aux clock source missing or invalid\n");
> fallthrough;
> case IMX7D:
> + case IMX7D_EP:
> if (dbi_base->start == IMX8MQ_PCIE2_BASE_ADDR)
> imx6_pcie->controller_id = 1;
>
> @@ -1572,6 +1581,12 @@ static const struct imx6_pcie_drvdata drvdata[] = {
> .flags = IMX6_PCIE_FLAG_SUPPORTS_SUSPEND,
> .gpr = "fsl,imx7d-iomuxc-gpr",
> },
> + [IMX7D_EP] = {
> + .variant = IMX7D_EP,
> + .mode = DW_PCIE_EP_TYPE,
> + .gpr = "fsl,imx7d-iomuxc-gpr",
> + .epc_features = &imx6q_pcie_epc_features,
> + },
> [IMX8MQ] = {
> .variant = IMX8MQ,
> .gpr = "fsl,imx8mq-iomuxc-gpr",
> @@ -1611,6 +1626,7 @@ static const struct of_device_id imx6_pcie_of_match[] = {
> { .compatible = "fsl,imx6qp-pcie", .data = &drvdata[IMX6QP], },
> { .compatible = "fsl,imx6qp-pcie-ep", .data = &drvdata[IMX6QP_EP], },
> { .compatible = "fsl,imx7d-pcie", .data = &drvdata[IMX7D], },
> + { .compatible = "fsl,imx7d-pcie-ep", .data = &drvdata[IMX7D_EP], },
> { .compatible = "fsl,imx8mq-pcie", .data = &drvdata[IMX8MQ], },
> { .compatible = "fsl,imx8mm-pcie", .data = &drvdata[IMX8MM], },
> { .compatible = "fsl,imx8mp-pcie", .data = &drvdata[IMX8MP], },
> --
> 2.34.1
>
--
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