Hi,
This series adds support for PWM controller on new
Allwinner's SoCs, such as D1, T113s and R329. The implemented driver
provides basic functionality for control PWM channels.
v2:
- fix dt-bindings
- fix a remark in the driver
v3:
- fix dt-bindings
- fix sunxi-d1s-t113.dtsi
v4:
- fix a remark in the driver
Aleksandr Shubin (3):
dt-bindings: pwm: Add binding for Allwinner D1/T113-S3/R329 PWM
controller
pwm: Add Allwinner's D1/T113-S3/R329 SoCs PWM support
riscv: dts: allwinner: d1: Add pwm node
.../bindings/pwm/allwinner,sun20i-pwm.yaml | 86 +++++
.../boot/dts/allwinner/sunxi-d1s-t113.dtsi | 11 +
drivers/pwm/Kconfig | 10 +
drivers/pwm/Makefile | 1 +
drivers/pwm/pwm-sun20i.c | 323 ++++++++++++++++++
5 files changed, 431 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pwm/allwinner,sun20i-pwm.yaml
create mode 100644 drivers/pwm/pwm-sun20i.c
--
2.25.1
Allwinner's D1, T113-S3 and R329 SoCs have a quite different PWM
controllers with ones supported by pwm-sun4i driver.
This patch adds a PWM controller driver for Allwinner's D1,
T113-S3 and R329 SoCs. The main difference between these SoCs
is the number of channels defined by the DT property.
Signed-off-by: Aleksandr Shubin <[email protected]>
---
drivers/pwm/Kconfig | 10 ++
drivers/pwm/Makefile | 1 +
drivers/pwm/pwm-sun20i.c | 323 +++++++++++++++++++++++++++++++++++++++
3 files changed, 334 insertions(+)
create mode 100644 drivers/pwm/pwm-sun20i.c
diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig
index 8df861b1f4a3..05c48a36969e 100644
--- a/drivers/pwm/Kconfig
+++ b/drivers/pwm/Kconfig
@@ -594,6 +594,16 @@ config PWM_SUN4I
To compile this driver as a module, choose M here: the module
will be called pwm-sun4i.
+config PWM_SUN20I
+ tristate "Allwinner D1/T113s/R329 PWM support"
+ depends on ARCH_SUNXI || COMPILE_TEST
+ depends on COMMON_CLK
+ help
+ Generic PWM framework driver for Allwinner D1/T113s/R329 SoCs.
+
+ To compile this driver as a module, choose M here: the module
+ will be called pwm-sun20i.
+
config PWM_SUNPLUS
tristate "Sunplus PWM support"
depends on ARCH_SUNPLUS || COMPILE_TEST
diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile
index 19899b912e00..cea872e22c78 100644
--- a/drivers/pwm/Makefile
+++ b/drivers/pwm/Makefile
@@ -55,6 +55,7 @@ obj-$(CONFIG_PWM_STM32) += pwm-stm32.o
obj-$(CONFIG_PWM_STM32_LP) += pwm-stm32-lp.o
obj-$(CONFIG_PWM_STMPE) += pwm-stmpe.o
obj-$(CONFIG_PWM_SUN4I) += pwm-sun4i.o
+obj-$(CONFIG_PWM_SUN20I) += pwm-sun20i.o
obj-$(CONFIG_PWM_SUNPLUS) += pwm-sunplus.o
obj-$(CONFIG_PWM_TEGRA) += pwm-tegra.o
obj-$(CONFIG_PWM_TIECAP) += pwm-tiecap.o
diff --git a/drivers/pwm/pwm-sun20i.c b/drivers/pwm/pwm-sun20i.c
new file mode 100644
index 000000000000..e2d425b64066
--- /dev/null
+++ b/drivers/pwm/pwm-sun20i.c
@@ -0,0 +1,323 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * PWM Controller Driver for sunxi platforms (D1, T113-S3 and R329)
+ *
+ * Limitations:
+ * - When the parameters change, current running period will not be completed
+ * and run new settings immediately.
+ * - It output HIGH-Z state when PWM channel disabled.
+ *
+ * Copyright (c) 2023 Aleksandr Shubin <[email protected]>
+ */
+
+#include <linux/bitfield.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/pwm.h>
+#include <linux/reset.h>
+
+#define PWM_CLK_CFG(chan) (0x20 + (((chan) >> 1) * 0x4))
+#define PWM_CLK_CFG_SRC GENMASK(8, 7)
+#define PWM_CLK_CFG_DIV_M GENMASK(3, 0)
+
+#define PWM_CLK_GATE 0x40
+#define PWM_CLK_GATE_BYPASS(chan) BIT((chan) - 16)
+#define PWM_CLK_GATE_GATING(chan) BIT(chan)
+
+#define PWM_ENABLE 0x80
+#define PWM_ENABLE_EN(chan) BIT(chan)
+
+#define PWM_CTL(chan) (0x100 + (chan) * 0x20)
+#define PWM_CTL_ACT_STA BIT(8)
+#define PWM_CTL_PRESCAL_K GENMASK(7, 0)
+
+#define PWM_PERIOD(chan) (0x104 + (chan) * 0x20)
+#define PWM_PERIOD_ENTIRE_CYCLE GENMASK(31, 16)
+#define PWM_PERIOD_ACT_CYCLE GENMASK(15, 0)
+
+#define PWM_MAGIC (255 * 65535 + 2 * 65534 + 1)
+
+struct sun20i_pwm_chip {
+ struct clk *clk_bus, *clk_hosc;
+ struct reset_control *rst;
+ struct pwm_chip chip;
+ void __iomem *base;
+ /* Mutex to protect pwm apply state */
+ struct mutex mutex;
+};
+
+static inline struct sun20i_pwm_chip *to_sun20i_pwm_chip(struct pwm_chip *chip)
+{
+ return container_of(chip, struct sun20i_pwm_chip, chip);
+}
+
+static inline u32 sun20i_pwm_readl(struct sun20i_pwm_chip *chip,
+ unsigned long offset)
+{
+ return readl(chip->base + offset);
+}
+
+static inline void sun20i_pwm_writel(struct sun20i_pwm_chip *chip,
+ u32 val, unsigned long offset)
+{
+ writel(val, chip->base + offset);
+}
+
+static int sun20i_pwm_get_state(struct pwm_chip *chip,
+ struct pwm_device *pwm,
+ struct pwm_state *state)
+{
+ struct sun20i_pwm_chip *sun20i_chip = to_sun20i_pwm_chip(chip);
+ u16 ent_cycle, act_cycle, prescal;
+ u64 clk_rate, tmp;
+ u8 div_id;
+ u32 val;
+
+ mutex_lock(&sun20i_chip->mutex);
+
+ val = sun20i_pwm_readl(sun20i_chip, PWM_CLK_CFG(pwm->hwpwm));
+ div_id = FIELD_GET(PWM_CLK_CFG_DIV_M, val);
+ if (FIELD_GET(PWM_CLK_CFG_SRC, val) == 0)
+ clk_rate = clk_get_rate(sun20i_chip->clk_hosc);
+ else
+ clk_rate = clk_get_rate(sun20i_chip->clk_bus);
+
+ val = sun20i_pwm_readl(sun20i_chip, PWM_CTL(pwm->hwpwm));
+ state->polarity = (PWM_CTL_ACT_STA & val) ? PWM_POLARITY_NORMAL : PWM_POLARITY_INVERSED;
+
+ prescal = FIELD_GET(PWM_CTL_PRESCAL_K, val) + 1;
+
+ val = sun20i_pwm_readl(sun20i_chip, PWM_ENABLE);
+ state->enabled = (PWM_ENABLE_EN(pwm->hwpwm) & val) ? true : false;
+
+ val = sun20i_pwm_readl(sun20i_chip, PWM_PERIOD(pwm->hwpwm));
+ act_cycle = FIELD_GET(PWM_PERIOD_ACT_CYCLE, val);
+ ent_cycle = FIELD_GET(PWM_PERIOD_ENTIRE_CYCLE, val);
+
+ /*
+ * The duration of the active phase should not be longer
+ * than the duration of the period
+ */
+ if (act_cycle > ent_cycle)
+ act_cycle = ent_cycle;
+
+ tmp = ((u64)(act_cycle) * prescal << div_id) * NSEC_PER_SEC;
+ state->duty_cycle = DIV_ROUND_UP_ULL(tmp, clk_rate);
+ tmp = ((u64)(ent_cycle) * prescal << div_id) * NSEC_PER_SEC;
+ state->period = DIV_ROUND_UP_ULL(tmp, clk_rate);
+ mutex_unlock(&sun20i_chip->mutex);
+
+ return 0;
+}
+
+static int sun20i_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
+ const struct pwm_state *state)
+{
+ struct sun20i_pwm_chip *sun20i_chip = to_sun20i_pwm_chip(chip);
+ u32 clk_gate, clk_cfg, pwm_en, ctl, period;
+ u64 bus_rate, hosc_rate, clk_div, val, tmp;
+ u32 prescaler, div_m;
+ bool use_bus_clk;
+ int ret = 0;
+
+ mutex_lock(&sun20i_chip->mutex);
+
+ pwm_en = sun20i_pwm_readl(sun20i_chip, PWM_ENABLE);
+
+ if (state->enabled != pwm->state.enabled)
+ clk_gate = sun20i_pwm_readl(sun20i_chip, PWM_CLK_GATE);
+
+ if (state->enabled != pwm->state.enabled && !state->enabled) {
+ clk_gate &= ~PWM_CLK_GATE_GATING(pwm->hwpwm);
+ pwm_en &= ~PWM_ENABLE_EN(pwm->hwpwm);
+ sun20i_pwm_writel(sun20i_chip, pwm_en, PWM_ENABLE);
+ sun20i_pwm_writel(sun20i_chip, clk_gate, PWM_CLK_GATE);
+ }
+
+ if (state->polarity != pwm->state.polarity ||
+ state->duty_cycle != pwm->state.duty_cycle ||
+ state->period != pwm->state.period) {
+ ctl = sun20i_pwm_readl(sun20i_chip, PWM_CTL(pwm->hwpwm));
+ clk_cfg = sun20i_pwm_readl(sun20i_chip, PWM_CLK_CFG(pwm->hwpwm));
+ hosc_rate = clk_get_rate(sun20i_chip->clk_hosc);
+ bus_rate = clk_get_rate(sun20i_chip->clk_bus);
+ if (pwm_en & PWM_ENABLE_EN(pwm->hwpwm ^ 1)) {
+ /* if the neighbor channel is enable, check period only */
+ use_bus_clk = FIELD_GET(PWM_CLK_CFG_SRC, clk_cfg) != 0;
+ val = state->period * (use_bus_clk ? bus_rate : hosc_rate);
+ do_div(val, NSEC_PER_SEC);
+
+ div_m = FIELD_GET(PWM_CLK_CFG_DIV_M, clk_cfg);
+ } else {
+ /* check period and select clock source */
+ use_bus_clk = false;
+ val = state->period * hosc_rate;
+ do_div(val, NSEC_PER_SEC);
+ if (val <= 1) {
+ use_bus_clk = true;
+ val = state->period * bus_rate;
+ do_div(val, NSEC_PER_SEC);
+ if (val <= 1) {
+ ret = -EINVAL;
+ goto unlock_mutex;
+ }
+ }
+ div_m = fls(DIV_ROUND_DOWN_ULL(val, PWM_MAGIC));
+ if (div_m >= 9) {
+ ret = -EINVAL;
+ goto unlock_mutex;
+ }
+
+ /* set up the CLK_DIV_M and clock CLK_SRC */
+ clk_cfg = FIELD_PREP(PWM_CLK_CFG_DIV_M, div_m);
+ clk_cfg |= FIELD_PREP(PWM_CLK_CFG_SRC, use_bus_clk);
+
+ sun20i_pwm_writel(sun20i_chip, clk_cfg, PWM_CLK_CFG(pwm->hwpwm));
+ }
+
+ /* calculate prescaler, PWM entire cycle */
+ clk_div = val >> div_m;
+ if (clk_div <= 65534) {
+ prescaler = 0;
+ } else {
+ prescaler = DIV_ROUND_UP_ULL(clk_div - 65534, 65535);
+ if (prescaler >= 256) {
+ ret = -EINVAL;
+ goto unlock_mutex;
+ }
+ do_div(clk_div, prescaler + 1);
+ }
+
+ period = FIELD_PREP(PWM_PERIOD_ENTIRE_CYCLE, clk_div);
+
+ /* set duty cycle */
+ val = state->duty_cycle * (use_bus_clk ? bus_rate : hosc_rate);
+ do_div(val, NSEC_PER_SEC);
+ clk_div = val >> div_m;
+ do_div(clk_div, prescaler + 1);
+
+ /*
+ * The formula of the output period and the duty-cycle for PWM are as follows.
+ * T period = (PWM01_CLK / PWM0_PRESCALE_K)^-1 * (PPR0.PWM_ENTIRE_CYCLE + 1)
+ * T high-level = (PWM01_CLK / PWM0_PRESCALE_K)^-1 * PPR0.PWM_ACT_CYCLE
+ * Duty-cycle = T high-level / T period
+ * In accordance with this formula, in order to set the duty-cycle to 100%,
+ * it is necessary that PWM_ACT_CYCLE >= PWM_ENTIRE_CYCLE + 1
+ */
+ if (state->duty_cycle == state->period)
+ clk_div++;
+ period |= FIELD_PREP(PWM_PERIOD_ACT_CYCLE, clk_div);
+ sun20i_pwm_writel(sun20i_chip, period, PWM_PERIOD(pwm->hwpwm));
+
+ ctl = FIELD_PREP(PWM_CTL_PRESCAL_K, prescaler);
+ if (state->polarity == PWM_POLARITY_NORMAL)
+ ctl |= PWM_CTL_ACT_STA;
+
+ sun20i_pwm_writel(sun20i_chip, ctl, PWM_CTL(pwm->hwpwm));
+ }
+
+ if (state->enabled != pwm->state.enabled && state->enabled) {
+ clk_gate &= ~PWM_CLK_GATE_BYPASS(pwm->hwpwm);
+ clk_gate |= PWM_CLK_GATE_GATING(pwm->hwpwm);
+ pwm_en |= PWM_ENABLE_EN(pwm->hwpwm);
+ sun20i_pwm_writel(sun20i_chip, pwm_en, PWM_ENABLE);
+ sun20i_pwm_writel(sun20i_chip, clk_gate, PWM_CLK_GATE);
+ }
+
+unlock_mutex:
+ mutex_unlock(&sun20i_chip->mutex);
+
+ return ret;
+}
+
+static const struct pwm_ops sun20i_pwm_ops = {
+ .get_state = sun20i_pwm_get_state,
+ .apply = sun20i_pwm_apply,
+ .owner = THIS_MODULE,
+};
+
+static const struct of_device_id sun20i_pwm_dt_ids[] = {
+ { .compatible = "allwinner,sun20i-d1-pwm" },
+ { },
+};
+MODULE_DEVICE_TABLE(of, sun20i_pwm_dt_ids);
+
+static int sun20i_pwm_probe(struct platform_device *pdev)
+{
+ struct sun20i_pwm_chip *sun20i_chip;
+ int ret;
+
+ sun20i_chip = devm_kzalloc(&pdev->dev, sizeof(*sun20i_chip), GFP_KERNEL);
+ if (!sun20i_chip)
+ return -ENOMEM;
+
+ sun20i_chip->base = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(sun20i_chip->base))
+ return PTR_ERR(sun20i_chip->base);
+
+ sun20i_chip->clk_bus = devm_clk_get_enabled(&pdev->dev, "bus");
+ if (IS_ERR(sun20i_chip->clk_bus))
+ return dev_err_probe(&pdev->dev, PTR_ERR(sun20i_chip->clk_bus),
+ "failed to get bus clock\n");
+
+ sun20i_chip->clk_hosc = devm_clk_get_enabled(&pdev->dev, "hosc");
+ if (IS_ERR(sun20i_chip->clk_hosc))
+ return dev_err_probe(&pdev->dev, PTR_ERR(sun20i_chip->clk_hosc),
+ "failed to get hosc clock\n");
+
+ sun20i_chip->rst = devm_reset_control_get_exclusive(&pdev->dev, NULL);
+ if (IS_ERR(sun20i_chip->rst))
+ return dev_err_probe(&pdev->dev, PTR_ERR(sun20i_chip->rst),
+ "failed to get bus reset\n");
+
+ ret = of_property_read_u32(pdev->dev.of_node, "allwinner,pwm-channels",
+ &sun20i_chip->chip.npwm);
+ if (ret)
+ sun20i_chip->chip.npwm = 8;
+
+ /* Deassert reset */
+ ret = reset_control_deassert(sun20i_chip->rst);
+ if (ret)
+ return dev_err_probe(&pdev->dev, ret, "failed to deassert reset\n");
+
+ sun20i_chip->chip.dev = &pdev->dev;
+ sun20i_chip->chip.ops = &sun20i_pwm_ops;
+
+ mutex_init(&sun20i_chip->mutex);
+
+ ret = pwmchip_add(&sun20i_chip->chip);
+ if (ret < 0) {
+ reset_control_assert(sun20i_chip->rst);
+ return dev_err_probe(&pdev->dev, ret, "failed to add PWM chip\n");
+ }
+
+ platform_set_drvdata(pdev, sun20i_chip);
+
+ return 0;
+}
+
+static void sun20i_pwm_remove(struct platform_device *pdev)
+{
+ struct sun20i_pwm_chip *sun20i_chip = platform_get_drvdata(pdev);
+
+ pwmchip_remove(&sun20i_chip->chip);
+
+ reset_control_assert(sun20i_chip->rst);
+}
+
+static struct platform_driver sun20i_pwm_driver = {
+ .driver = {
+ .name = "sun20i-pwm",
+ .of_match_table = sun20i_pwm_dt_ids,
+ },
+ .probe = sun20i_pwm_probe,
+ .remove_new = sun20i_pwm_remove,
+};
+module_platform_driver(sun20i_pwm_driver);
+
+MODULE_AUTHOR("Aleksandr Shubin <[email protected]>");
+MODULE_DESCRIPTION("Allwinner sun20i PWM driver");
+MODULE_LICENSE("GPL");
--
2.25.1
D1 and T113s contain a pwm controller with 8 channels.
This controller is supported by the sun20i-pwm driver.
Add a device tree node for it.
Signed-off-by: Aleksandr Shubin <[email protected]>
---
arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi b/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi
index 922e8e0e2c09..e24543b6aff7 100644
--- a/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi
+++ b/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi
@@ -127,6 +127,17 @@ uart3_pb_pins: uart3-pb-pins {
};
};
+ pwm: pwm@2000c00 {
+ compatible = "allwinner,sun20i-d1-pwm";
+ reg = <0x02000c00 0x400>;
+ clocks = <&dcxo>,
+ <&ccu CLK_BUS_PWM>;
+ clock-names = "hosc", "bus";
+ resets = <&ccu RST_BUS_PWM>;
+ status = "disabled";
+ #pwm-cells = <0x3>;
+ };
+
ccu: clock-controller@2001000 {
compatible = "allwinner,sun20i-d1-ccu";
reg = <0x2001000 0x1000>;
--
2.25.1
Hi Aleksandr,
kernel test robot noticed the following build warnings:
[auto build test WARNING on thierry-reding-pwm/for-next]
[also build test WARNING on sunxi/sunxi/for-next robh/for-next linus/master v6.5-rc5 next-20230809]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Aleksandr-Shubin/dt-bindings-pwm-Add-binding-for-Allwinner-D1-T113-S3-R329-PWM-controller/20230810-225849
base: https://git.kernel.org/pub/scm/linux/kernel/git/thierry.reding/linux-pwm.git for-next
patch link: https://lore.kernel.org/r/20230810145443.1053387-3-privatesub2%40gmail.com
patch subject: [PATCH v4 2/3] pwm: Add Allwinner's D1/T113-S3/R329 SoCs PWM support
config: x86_64-allyesconfig (https://download.01.org/0day-ci/archive/20230812/[email protected]/config)
compiler: gcc-12 (Debian 12.2.0-14) 12.2.0
reproduce: (https://download.01.org/0day-ci/archive/20230812/[email protected]/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <[email protected]>
| Closes: https://lore.kernel.org/oe-kbuild-all/[email protected]/
All warnings (new ones prefixed by >>):
drivers/pwm/pwm-sun20i.c: In function 'sun20i_pwm_apply':
>> drivers/pwm/pwm-sun20i.c:121:48: warning: unused variable 'tmp' [-Wunused-variable]
121 | u64 bus_rate, hosc_rate, clk_div, val, tmp;
| ^~~
vim +/tmp +121 drivers/pwm/pwm-sun20i.c
115
116 static int sun20i_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
117 const struct pwm_state *state)
118 {
119 struct sun20i_pwm_chip *sun20i_chip = to_sun20i_pwm_chip(chip);
120 u32 clk_gate, clk_cfg, pwm_en, ctl, period;
> 121 u64 bus_rate, hosc_rate, clk_div, val, tmp;
122 u32 prescaler, div_m;
123 bool use_bus_clk;
124 int ret = 0;
125
126 mutex_lock(&sun20i_chip->mutex);
127
128 pwm_en = sun20i_pwm_readl(sun20i_chip, PWM_ENABLE);
129
130 if (state->enabled != pwm->state.enabled)
131 clk_gate = sun20i_pwm_readl(sun20i_chip, PWM_CLK_GATE);
132
133 if (state->enabled != pwm->state.enabled && !state->enabled) {
134 clk_gate &= ~PWM_CLK_GATE_GATING(pwm->hwpwm);
135 pwm_en &= ~PWM_ENABLE_EN(pwm->hwpwm);
136 sun20i_pwm_writel(sun20i_chip, pwm_en, PWM_ENABLE);
137 sun20i_pwm_writel(sun20i_chip, clk_gate, PWM_CLK_GATE);
138 }
139
140 if (state->polarity != pwm->state.polarity ||
141 state->duty_cycle != pwm->state.duty_cycle ||
142 state->period != pwm->state.period) {
143 ctl = sun20i_pwm_readl(sun20i_chip, PWM_CTL(pwm->hwpwm));
144 clk_cfg = sun20i_pwm_readl(sun20i_chip, PWM_CLK_CFG(pwm->hwpwm));
145 hosc_rate = clk_get_rate(sun20i_chip->clk_hosc);
146 bus_rate = clk_get_rate(sun20i_chip->clk_bus);
147 if (pwm_en & PWM_ENABLE_EN(pwm->hwpwm ^ 1)) {
148 /* if the neighbor channel is enable, check period only */
149 use_bus_clk = FIELD_GET(PWM_CLK_CFG_SRC, clk_cfg) != 0;
150 val = state->period * (use_bus_clk ? bus_rate : hosc_rate);
151 do_div(val, NSEC_PER_SEC);
152
153 div_m = FIELD_GET(PWM_CLK_CFG_DIV_M, clk_cfg);
154 } else {
155 /* check period and select clock source */
156 use_bus_clk = false;
157 val = state->period * hosc_rate;
158 do_div(val, NSEC_PER_SEC);
159 if (val <= 1) {
160 use_bus_clk = true;
161 val = state->period * bus_rate;
162 do_div(val, NSEC_PER_SEC);
163 if (val <= 1) {
164 ret = -EINVAL;
165 goto unlock_mutex;
166 }
167 }
168 div_m = fls(DIV_ROUND_DOWN_ULL(val, PWM_MAGIC));
169 if (div_m >= 9) {
170 ret = -EINVAL;
171 goto unlock_mutex;
172 }
173
174 /* set up the CLK_DIV_M and clock CLK_SRC */
175 clk_cfg = FIELD_PREP(PWM_CLK_CFG_DIV_M, div_m);
176 clk_cfg |= FIELD_PREP(PWM_CLK_CFG_SRC, use_bus_clk);
177
178 sun20i_pwm_writel(sun20i_chip, clk_cfg, PWM_CLK_CFG(pwm->hwpwm));
179 }
180
181 /* calculate prescaler, PWM entire cycle */
182 clk_div = val >> div_m;
183 if (clk_div <= 65534) {
184 prescaler = 0;
185 } else {
186 prescaler = DIV_ROUND_UP_ULL(clk_div - 65534, 65535);
187 if (prescaler >= 256) {
188 ret = -EINVAL;
189 goto unlock_mutex;
190 }
191 do_div(clk_div, prescaler + 1);
192 }
193
194 period = FIELD_PREP(PWM_PERIOD_ENTIRE_CYCLE, clk_div);
195
196 /* set duty cycle */
197 val = state->duty_cycle * (use_bus_clk ? bus_rate : hosc_rate);
198 do_div(val, NSEC_PER_SEC);
199 clk_div = val >> div_m;
200 do_div(clk_div, prescaler + 1);
201
202 /*
203 * The formula of the output period and the duty-cycle for PWM are as follows.
204 * T period = (PWM01_CLK / PWM0_PRESCALE_K)^-1 * (PPR0.PWM_ENTIRE_CYCLE + 1)
205 * T high-level = (PWM01_CLK / PWM0_PRESCALE_K)^-1 * PPR0.PWM_ACT_CYCLE
206 * Duty-cycle = T high-level / T period
207 * In accordance with this formula, in order to set the duty-cycle to 100%,
208 * it is necessary that PWM_ACT_CYCLE >= PWM_ENTIRE_CYCLE + 1
209 */
210 if (state->duty_cycle == state->period)
211 clk_div++;
212 period |= FIELD_PREP(PWM_PERIOD_ACT_CYCLE, clk_div);
213 sun20i_pwm_writel(sun20i_chip, period, PWM_PERIOD(pwm->hwpwm));
214
215 ctl = FIELD_PREP(PWM_CTL_PRESCAL_K, prescaler);
216 if (state->polarity == PWM_POLARITY_NORMAL)
217 ctl |= PWM_CTL_ACT_STA;
218
219 sun20i_pwm_writel(sun20i_chip, ctl, PWM_CTL(pwm->hwpwm));
220 }
221
222 if (state->enabled != pwm->state.enabled && state->enabled) {
223 clk_gate &= ~PWM_CLK_GATE_BYPASS(pwm->hwpwm);
224 clk_gate |= PWM_CLK_GATE_GATING(pwm->hwpwm);
225 pwm_en |= PWM_ENABLE_EN(pwm->hwpwm);
226 sun20i_pwm_writel(sun20i_chip, pwm_en, PWM_ENABLE);
227 sun20i_pwm_writel(sun20i_chip, clk_gate, PWM_CLK_GATE);
228 }
229
230 unlock_mutex:
231 mutex_unlock(&sun20i_chip->mutex);
232
233 return ret;
234 }
235
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki