bootph-all phase tag was added to dt-schema (dtschema/schemas/bootph.yaml)
to overcome u-boot dts challenges.
Add bootph-all property for all the nodes that are used in the SPL stage
along with later boot stages.
This series will be ported to the u-boot k3-j784s4 support patch series
for syncing, and was requested in its review process:
https://lore.kernel.org/u-boot/20230321155227.GV8135@bill-the-cat/
v3: Changelog:
1) Changed all the bootph-pre-ram to bootph-all, as only
secure_proxy_mcu and secure_proxy_sa3 are exclusively used by R5 SPL.
Rest of the nodes are also used by later boot stages.
2) Merged SoC dtsi changes in single patch.
3) Moved cbass_main and cbass_mcu_wkup bootph-all to k3-j784s4.dtsi
Link to v2:
https://lore.kernel.org/lkml/[email protected]/#t
v2 Changelog :
1) Added k3-am69-sk.dts bootph-pre-ram patch
2) Added bootph-pre-ram for wkup_pmx0 and ospi0
3) Added bootph-pre-ram for mcu_timer1
Link to v1:
https://lore.kernel.org/linux-arm-kernel/[email protected]/
Apurva Nandan (3):
arm64: dts: ti: k3-j784s4: Add bootph-all property
arm64: dts: ti: k3-j784s4-evm: Add bootph-all property
arm64: dts: ti: k3-am69-sk: Add bootph-all property
arch/arm64/boot/dts/ti/k3-am69-sk.dts | 13 ++++++++++
arch/arm64/boot/dts/ti/k3-j784s4-evm.dts | 25 +++++++++++++++++++
arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 2 ++
.../boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi | 9 +++++++
arch/arm64/boot/dts/ti/k3-j784s4.dtsi | 2 ++
5 files changed, 51 insertions(+)
--
2.34.1
On 00:12-20230811, Apurva Nandan wrote:
> bootph-all phase tag was added to dt-schema (dtschema/schemas/bootph.yaml)
> to overcome u-boot dts challenges.
>
> Add bootph-all property for all the nodes that are used in the SPL stage
> along with later boot stages.
>
> This series will be ported to the u-boot k3-j784s4 support patch series
> for syncing, and was requested in its review process:
> https://lore.kernel.org/u-boot/20230321155227.GV8135@bill-the-cat/
>
> v3: Changelog:
> 1) Changed all the bootph-pre-ram to bootph-all, as only
> secure_proxy_mcu and secure_proxy_sa3 are exclusively used by R5 SPL.
> Rest of the nodes are also used by later boot stages.
> 2) Merged SoC dtsi changes in single patch.
> 3) Moved cbass_main and cbass_mcu_wkup bootph-all to k3-j784s4.dtsi
[...]
> Apurva Nandan (3):
> arm64: dts: ti: k3-j784s4: Add bootph-all property
> arm64: dts: ti: k3-j784s4-evm: Add bootph-all property
> arm64: dts: ti: k3-am69-sk: Add bootph-all property
Follow https://lore.kernel.org/all/48b554aef75d11e6ad2ef7d21f22accb35432112.1683034376.git.michal.simek@amd.com/
for example of proper commit message and subject line.
The patch content actually is easy to read since it is adding
bootph-all property - but we do have a few exceptions. Commit message
should explain the rational of the choices made. For example, you
probably need to use secure_proxy_sa3 to talk with tifs in-order to
boot and that is a pre-ram property and so on..
So, nice refresh in the right direction, but a bit more work to do.
Thanks for handling am69-sk :)..
--
Regards,
Nishanth Menon
Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3 1A34 DDB5 849D 1736 249D
Add bootph-all property for all the nodes that are used in SPL stage
along with later boot stages.
These bootph-all properties will be synced later to u-boot j784s4 dts.
Signed-off-by: Apurva Nandan <[email protected]>
---
arch/arm64/boot/dts/ti/k3-j784s4-evm.dts | 25 ++++++++++++++++++++++++
1 file changed, 25 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts
index edc1009b2d1e..47d41d60e49a 100644
--- a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts
+++ b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts
@@ -252,7 +252,9 @@ vdd_sd_dv: regulator-TLV71033 {
};
&main_pmx0 {
+ bootph-all;
main_uart8_pins_default: main-uart8-default-pins {
+ bootph-all;
pinctrl-single,pins = <
J784S4_IOPAD(0x040, PIN_INPUT, 14) /* (AF37) MCASP0_AXR0.UART8_CTSn */
J784S4_IOPAD(0x044, PIN_OUTPUT, 14) /* (AG37) MCASP0_AXR1.UART8_RTSn */
@@ -269,6 +271,7 @@ J784S4_IOPAD(0x0e4, PIN_INPUT_PULLUP, 0) /* (AP37) I2C0_SDA */
};
main_mmc1_pins_default: main-mmc1-default-pins {
+ bootph-all;
pinctrl-single,pins = <
J784S4_IOPAD(0x104, PIN_INPUT, 0) /* (AB38) MMC1_CLK */
J784S4_IOPAD(0x108, PIN_INPUT, 0) /* (AB36) MMC1_CMD */
@@ -289,7 +292,9 @@ J784S4_IOPAD(0x020, PIN_INPUT, 7) /* (AJ35) MCAN15_RX.GPIO0_8 */
};
&wkup_pmx2 {
+ bootph-all;
wkup_uart0_pins_default: wkup-uart0-default-pins {
+ bootph-all;
pinctrl-single,pins = <
J721S2_WKUP_IOPAD(0x070, PIN_INPUT, 0) /* (L37) WKUP_GPIO0_6.WKUP_UART0_CTSn */
J721S2_WKUP_IOPAD(0x074, PIN_INPUT, 0) /* (L36) WKUP_GPIO0_7.WKUP_UART0_RTSn */
@@ -299,6 +304,7 @@ J721S2_WKUP_IOPAD(0x04c, PIN_INPUT, 0) /* (K34) WKUP_UART0_TXD */
};
wkup_i2c0_pins_default: wkup-i2c0-default-pins {
+ bootph-all;
pinctrl-single,pins = <
J721S2_WKUP_IOPAD(0x98, PIN_INPUT, 0) /* (N33) WKUP_I2C0_SCL */
J721S2_WKUP_IOPAD(0x9c, PIN_INPUT, 0) /* (N35) WKUP_I2C0_SDA */
@@ -306,6 +312,7 @@ J721S2_WKUP_IOPAD(0x9c, PIN_INPUT, 0) /* (N35) WKUP_I2C0_SDA */
};
mcu_uart0_pins_default: mcu-uart0-default-pins {
+ bootph-all;
pinctrl-single,pins = <
J784S4_WKUP_IOPAD(0x090, PIN_INPUT, 0) /* (H37) WKUP_GPIO0_14.MCU_UART0_CTSn */
J784S4_WKUP_IOPAD(0x094, PIN_OUTPUT, 0) /* (K37) WKUP_GPIO0_15.MCU_UART0_RTSn */
@@ -366,7 +373,9 @@ J784S4_WKUP_IOPAD(0x170, PIN_INPUT, 0) /* (Y36) MCU_ADC1_AIN7 */
};
&wkup_pmx0 {
+ bootph-all;
mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-default-pins {
+ bootph-all;
pinctrl-single,pins = <
J784S4_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (E32) MCU_OSPI0_CLK */
J784S4_WKUP_IOPAD(0x02c, PIN_OUTPUT, 0) /* (A32) MCU_OSPI0_CSn0 */
@@ -384,7 +393,9 @@ J784S4_WKUP_IOPAD(0x008, PIN_INPUT, 0) /* (C34) MCU_OSPI0_DQS */
};
&wkup_pmx1 {
+ bootph-all;
mcu_fss0_ospi0_1_pins_default: mcu-fss0-ospi0-1-default-pins {
+ bootph-all;
pinctrl-single,pins = <
J784S4_WKUP_IOPAD(0x004, PIN_OUTPUT, 6) /* (C32) MCU_OSPI0_ECC_FAIL */
J784S4_WKUP_IOPAD(0x000, PIN_OUTPUT, 6) /* (B34) MCU_OSPI0_RESET_OUT0 */
@@ -392,6 +403,7 @@ J784S4_WKUP_IOPAD(0x000, PIN_OUTPUT, 6) /* (B34) MCU_OSPI0_RESET_OUT0 */
};
mcu_fss0_ospi1_pins_default: mcu-fss0-ospi1-default-pins {
+ bootph-all;
pinctrl-single,pins = <
J784S4_WKUP_IOPAD(0x008, PIN_OUTPUT, 0) /* (F32) MCU_OSPI1_CLK */
J784S4_WKUP_IOPAD(0x024, PIN_OUTPUT, 0) /* (G32) MCU_OSPI1_CSn0 */
@@ -406,6 +418,7 @@ J784S4_WKUP_IOPAD(0x00C, PIN_INPUT, 0) /* (C31) MCU_OSPI1_LBCLKO */
};
&wkup_uart0 {
+ bootph-all;
/* Firmware usage */
status = "reserved";
pinctrl-names = "default";
@@ -413,6 +426,7 @@ &wkup_uart0 {
};
&wkup_i2c0 {
+ bootph-all;
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&wkup_i2c0_pins_default>;
@@ -426,12 +440,14 @@ eeprom@50 {
};
&mcu_uart0 {
+ bootph-all;
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&mcu_uart0_pins_default>;
};
&main_uart8 {
+ bootph-all;
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_uart8_pins_default>;
@@ -442,15 +458,18 @@ &ufs_wrapper {
};
&fss {
+ bootph-all;
status = "okay";
};
&ospi0 {
+ bootph-all;
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&mcu_fss0_ospi0_pins_default>, <&mcu_fss0_ospi0_1_pins_default>;
flash@0 {
+ bootph-all;
compatible = "jedec,spi-nor";
reg = <0x0>;
spi-tx-bus-width = <8>;
@@ -498,6 +517,7 @@ partition@800000 {
};
partition@3fc0000 {
+ bootph-all;
label = "ospi.phypattern";
reg = <0x3fc0000 0x40000>;
};
@@ -506,11 +526,13 @@ partition@3fc0000 {
};
&ospi1 {
+ bootph-all;
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&mcu_fss0_ospi1_pins_default>;
flash@0 {
+ bootph-all;
compatible = "jedec,spi-nor";
reg = <0x0>;
spi-tx-bus-width = <1>;
@@ -558,6 +580,7 @@ partition@800000 {
};
partition@3fc0000 {
+ bootph-all;
label = "qspi.phypattern";
reg = <0x3fc0000 0x40000>;
};
@@ -602,6 +625,7 @@ exp2: gpio@22 {
};
&main_sdhci0 {
+ bootph-all;
/* eMMC */
status = "okay";
non-removable;
@@ -610,6 +634,7 @@ &main_sdhci0 {
};
&main_sdhci1 {
+ bootph-all;
/* SD card */
status = "okay";
pinctrl-0 = <&main_mmc1_pins_default>;
--
2.34.1
bootph-all phase tag was added to dt-schema (dtschema/schemas/bootph.yaml)
to overcome u-boot dts challenges.
Add bootph-all property for all the nodes that are also used in SPL stage
along with later boot stages.
These bootph-all properties will be synced later to u-boot j784s4 dts.
Signed-off-by: Apurva Nandan <[email protected]>
---
arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 2 ++
arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi | 9 +++++++++
arch/arm64/boot/dts/ti/k3-j784s4.dtsi | 2 ++
3 files changed, 13 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
index a04c44708a09..65eca0990300 100644
--- a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
@@ -670,6 +670,7 @@ main_sdhci1: mmc@4fb0000 {
};
main_navss: bus@30000000 {
+ bootph-all;
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
@@ -705,6 +706,7 @@ main_udmass_inta: msi-controller@33d00000 {
};
secure_proxy_main: mailbox@32c00000 {
+ bootph-all;
compatible = "ti,am654-secure-proxy";
#mbox-cells = <1>;
reg-names = "target_data", "rt", "scfg";
diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi
index 740ee794d7b9..a394bef093b6 100644
--- a/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi
@@ -7,6 +7,7 @@
&cbass_mcu_wakeup {
sms: system-controller@44083000 {
+ bootph-all;
compatible = "ti,k2g-sci";
ti,host-id = <12>;
@@ -19,22 +20,26 @@ sms: system-controller@44083000 {
reg = <0x00 0x44083000 0x00 0x1000>;
k3_pds: power-controller {
+ bootph-all;
compatible = "ti,sci-pm-domain";
#power-domain-cells = <2>;
};
k3_clks: clock-controller {
+ bootph-all;
compatible = "ti,k2g-sci-clk";
#clock-cells = <2>;
};
k3_reset: reset-controller {
+ bootph-all;
compatible = "ti,sci-reset";
#reset-cells = <2>;
};
};
chipid@43000014 {
+ bootph-all;
compatible = "ti,am654-chipid";
reg = <0x00 0x43000014 0x00 0x4>;
};
@@ -161,6 +166,7 @@ mcu_timer0: timer@40400000 {
};
mcu_timer1: timer@40410000 {
+ bootph-all;
compatible = "ti,am654-timer";
reg = <0x00 0x40410000 0x00 0x400>;
interrupts = <GIC_SPI 817 IRQ_TYPE_LEVEL_HIGH>;
@@ -442,6 +448,7 @@ mcu_spi2: spi@40320000 {
};
mcu_navss: bus@28380000 {
+ bootph-all;
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
@@ -451,6 +458,7 @@ mcu_navss: bus@28380000 {
dma-ranges;
mcu_ringacc: ringacc@2b800000 {
+ bootph-all;
compatible = "ti,am654-navss-ringacc";
reg = <0x00 0x2b800000 0x00 0x400000>,
<0x00 0x2b000000 0x00 0x400000>,
@@ -465,6 +473,7 @@ mcu_ringacc: ringacc@2b800000 {
};
mcu_udmap: dma-controller@285c0000 {
+ bootph-all;
compatible = "ti,j721e-navss-mcu-udmap";
reg = <0x00 0x285c0000 0x00 0x100>,
<0x00 0x2a800000 0x00 0x40000>,
diff --git a/arch/arm64/boot/dts/ti/k3-j784s4.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4.dtsi
index 8b5974d92e33..4398c3a463e1 100644
--- a/arch/arm64/boot/dts/ti/k3-j784s4.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j784s4.dtsi
@@ -228,6 +228,7 @@ pmu: pmu {
};
cbass_main: bus@100000 {
+ bootph-all;
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
@@ -263,6 +264,7 @@ cbass_main: bus@100000 {
<0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>;
cbass_mcu_wakeup: bus@28380000 {
+ bootph-all;
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
--
2.34.1
Add bootph-all property for all the nodes that are used in SPL stage
along with later boot stages.
These bootph-all property will be synced later to u-boot k3-am69 dts.
Signed-off-by: Apurva Nandan <[email protected]>
---
arch/arm64/boot/dts/ti/k3-am69-sk.dts | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-am69-sk.dts b/arch/arm64/boot/dts/ti/k3-am69-sk.dts
index d282c2c633c1..2302d55c3fe7 100644
--- a/arch/arm64/boot/dts/ti/k3-am69-sk.dts
+++ b/arch/arm64/boot/dts/ti/k3-am69-sk.dts
@@ -110,7 +110,9 @@ vdd_sd_dv: regulator-tlv71033 {
};
&main_pmx0 {
+ bootph-all;
main_uart8_pins_default: main-uart8-default-pins {
+ bootph-all;
pinctrl-single,pins = <
J784S4_IOPAD(0x0d0, PIN_INPUT, 11) /* (AP38) SPI0_CS1.UART8_RXD */
J784S4_IOPAD(0x0d4, PIN_OUTPUT, 11) /* (AN38) SPI0_CLK.UART8_TXD */
@@ -125,6 +127,7 @@ J784S4_IOPAD(0x0e4, PIN_INPUT_PULLUP, 0) /* (AP37) I2C0_SDA */
};
main_mmc1_pins_default: main-mmc1-default-pins {
+ bootph-all;
pinctrl-single,pins = <
J784S4_IOPAD(0x104, PIN_INPUT, 0) /* (AB38) MMC1_CLK */
J784S4_IOPAD(0x108, PIN_INPUT, 0) /* (AB36) MMC1_CMD */
@@ -164,7 +167,9 @@ J784S4_IOPAD(0x004, PIN_INPUT, 7) /* (AG36) MCAN12_TX.GPIO0_1 */
};
&wkup_pmx2 {
+ bootph-all;
wkup_uart0_pins_default: wkup-uart0-default-pins {
+ bootph-all;
pinctrl-single,pins = <
J721S2_WKUP_IOPAD(0x070, PIN_INPUT, 0) /* (L37) WKUP_GPIO0_6.WKUP_UART0_CTSn */
J721S2_WKUP_IOPAD(0x074, PIN_INPUT, 0) /* (L36) WKUP_GPIO0_7.WKUP_UART0_RTSn */
@@ -174,6 +179,7 @@ J721S2_WKUP_IOPAD(0x04c, PIN_INPUT, 0) /* (K34) WKUP_UART0_TXD */
};
wkup_i2c0_pins_default: wkup-i2c0-default-pins {
+ bootph-all;
pinctrl-single,pins = <
J721S2_WKUP_IOPAD(0x98, PIN_INPUT, 0) /* (N33) WKUP_I2C0_SCL */
J721S2_WKUP_IOPAD(0x9c, PIN_INPUT, 0) /* (N35) WKUP_I2C0_SDA */
@@ -181,6 +187,7 @@ J721S2_WKUP_IOPAD(0x9c, PIN_INPUT, 0) /* (N35) WKUP_I2C0_SDA */
};
mcu_uart0_pins_default: mcu-uart0-default-pins {
+ bootph-all;
pinctrl-single,pins = <
J784S4_WKUP_IOPAD(0x08c, PIN_INPUT, 0) /* (K38) WKUP_GPIO0_13.MCU_UART0_RXD */
J784S4_WKUP_IOPAD(0x088, PIN_OUTPUT, 0) /* (J37) WKUP_GPIO0_12.MCU_UART0_TXD */
@@ -242,6 +249,7 @@ J784S4_WKUP_IOPAD(0x0, PIN_INPUT, 7) /* (M33) WKUP_GPIO0_49 */
};
&wkup_uart0 {
+ bootph-all;
/* Firmware usage */
status = "reserved";
pinctrl-names = "default";
@@ -249,6 +257,7 @@ &wkup_uart0 {
};
&wkup_i2c0 {
+ bootph-all;
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&wkup_i2c0_pins_default>;
@@ -268,6 +277,7 @@ &wkup_gpio0 {
};
&mcu_uart0 {
+ bootph-all;
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&mcu_uart0_pins_default>;
@@ -281,6 +291,7 @@ &mcu_i2c0 {
};
&main_uart8 {
+ bootph-all;
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_uart8_pins_default>;
@@ -307,6 +318,7 @@ exp1: gpio@21 {
};
&main_sdhci0 {
+ bootph-all;
/* eMMC */
status = "okay";
non-removable;
@@ -315,6 +327,7 @@ &main_sdhci0 {
};
&main_sdhci1 {
+ bootph-all;
/* SD card */
status = "okay";
pinctrl-0 = <&main_mmc1_pins_default>;
--
2.34.1