2023-08-11 13:10:05

by Yann Sionneau

[permalink] [raw]
Subject: [PATCH 1/2] i2c: designware: fix __i2c_dw_disable in case master is holding SCL low

From: Yann Sionneau <[email protected]>

The designware IP can be synthesized with the IC_EMPTYFIFO_HOLD_MASTER_EN
parameter.
In which case, if the TX FIFO gets empty and the last command didn't have
the STOP bit (IC_DATA_CMD[9]), the dw_apb_i2c will hold SCL low until
a new command is pushed into the TX FIFO or the transfer is aborted.

When the dw_apb_i2c is holding SCL low, it cannot be disabled.
The transfer must first be aborted.
Also, the bus recover won't work because SCL is held low by the master.

This patch checks if the master is holding SCL low in __i2c_dw_disable
before trying to disable the IP.
If SCL is held low, an abort is initiated.
When the abort is done, the disabling can then proceed.

This whole situation can happen for instance during SMBUS read data block
if the slave just responds with "byte count == 0".
This puts the master in an unrecoverable state, holding SCL low and the
current __i2c_dw_disable procedure is not working. In this situation
only a Linux reboot can fix the i2c bus.

Co-developed-by: Jonathan Borne <[email protected]>
Signed-off-by: Jonathan Borne <[email protected]>
Tested-by: Yann Sionneau <[email protected]>
Signed-off-by: Yann Sionneau <[email protected]>
---
drivers/i2c/busses/i2c-designware-common.c | 17 +++++++++++++++++
drivers/i2c/busses/i2c-designware-core.h | 3 +++
2 files changed, 20 insertions(+)

diff --git a/drivers/i2c/busses/i2c-designware-common.c b/drivers/i2c/busses/i2c-designware-common.c
index 9f8574320eb2..744927b0c5af 100644
--- a/drivers/i2c/busses/i2c-designware-common.c
+++ b/drivers/i2c/busses/i2c-designware-common.c
@@ -440,8 +440,25 @@ void __i2c_dw_disable(struct dw_i2c_dev *dev)
{
int timeout = 100;
u32 status;
+ u32 raw_intr_stats;
+ u32 enable;
+ bool abort_needed;
+ bool abort_done = false;
+
+ regmap_read(dev->map, DW_IC_RAW_INTR_STAT, &raw_intr_stats);
+ regmap_read(dev->map, DW_IC_ENABLE, &enable);
+
+ abort_needed = raw_intr_stats & DW_IC_INTR_MST_ON_HOLD;
+ if (abort_needed)
+ regmap_write(dev->map, DW_IC_ENABLE, enable | DW_IC_ENABLE_ABORT);

do {
+ if (abort_needed && !abort_done) {
+ regmap_read(dev->map, DW_IC_ENABLE, &enable);
+ abort_done = !(enable & DW_IC_ENABLE_ABORT);
+ continue;
+ }
+
__i2c_dw_disable_nowait(dev);
/*
* The enable status register may be unimplemented, but
diff --git a/drivers/i2c/busses/i2c-designware-core.h b/drivers/i2c/busses/i2c-designware-core.h
index 19ae23575945..dcd9bd9ee00f 100644
--- a/drivers/i2c/busses/i2c-designware-core.h
+++ b/drivers/i2c/busses/i2c-designware-core.h
@@ -98,6 +98,7 @@
#define DW_IC_INTR_START_DET BIT(10)
#define DW_IC_INTR_GEN_CALL BIT(11)
#define DW_IC_INTR_RESTART_DET BIT(12)
+#define DW_IC_INTR_MST_ON_HOLD BIT(13)

#define DW_IC_INTR_DEFAULT_MASK (DW_IC_INTR_RX_FULL | \
DW_IC_INTR_TX_ABRT | \
@@ -109,6 +110,8 @@
DW_IC_INTR_RX_UNDER | \
DW_IC_INTR_RD_REQ)

+#define DW_IC_ENABLE_ABORT BIT(1)
+
#define DW_IC_STATUS_ACTIVITY BIT(0)
#define DW_IC_STATUS_TFE BIT(2)
#define DW_IC_STATUS_MASTER_ACTIVITY BIT(5)
--
2.17.1



2023-08-11 13:28:41

by Yann Sionneau

[permalink] [raw]
Subject: [PATCH 2/2] i2c: designware: abort the transfer if receiving byte count of 0

From: Yann Sionneau <[email protected]>

Context:
It's not clear whether Linux SMBus stack supports receiving 0
as byte count for SMBus read data block.

Linux supports SMBus v2.0 spec, which says "The byte count may not be 0."
Which does not seem very clear to me, as a non-native speaker.
(Note that v3.0 of the spec says "The byte count may be 0.")

Some drivers explicitly return -EPROTO in case of byte count 0.

The issue:
Regardless of whether Linux supports byte count of 0, if this happens
the i2c-designware driver goes into an unrecoverable state holding
SCL low if the IP is synthesized with the IC_EMPTYFIFO_HOLD_MASTER_EN
parameter.

The fix proposed by this patch:
Abort the transfer by sending a STOP condition on the bus.

Another approach would be to ignore the issue and let the driver
timeout and disable the IP. The IP disabling is fixed by the previous
patch in this patch series.
The current patch just makes the recovery faster since Abort is sent
directly without waiting for the timeout to happen. With this patch,
disabling the IP is not necessary anymore.

Co-developed-by: Jonathan Borne <[email protected]>
Signed-off-by: Jonathan Borne <[email protected]>
Tested-by: Yann Sionneau <[email protected]>
Signed-off-by: Yann Sionneau <[email protected]>
---
drivers/i2c/busses/i2c-designware-master.c | 20 +++++++++++++++++---
1 file changed, 17 insertions(+), 3 deletions(-)

diff --git a/drivers/i2c/busses/i2c-designware-master.c b/drivers/i2c/busses/i2c-designware-master.c
index b55c19b2515a..fa5301566bb1 100644
--- a/drivers/i2c/busses/i2c-designware-master.c
+++ b/drivers/i2c/busses/i2c-designware-master.c
@@ -499,6 +499,15 @@ i2c_dw_recv_len(struct dw_i2c_dev *dev, u8 len)
return len;
}

+static void
+i2c_dw_abort(struct dw_i2c_dev *dev)
+{
+ u32 enable;
+
+ regmap_read(dev->map, DW_IC_ENABLE, &enable);
+ regmap_write(dev->map, DW_IC_ENABLE, enable | DW_IC_ENABLE_ABORT);
+}
+
static void
i2c_dw_read(struct dw_i2c_dev *dev)
{
@@ -526,11 +535,16 @@ i2c_dw_read(struct dw_i2c_dev *dev)
u32 flags = msgs[dev->msg_read_idx].flags;

regmap_read(dev->map, DW_IC_DATA_CMD, &tmp);
+ tmp &= DW_IC_DATA_CMD_DAT;
+
/* Ensure length byte is a valid value */
- if (flags & I2C_M_RECV_LEN &&
- (tmp & DW_IC_DATA_CMD_DAT) <= I2C_SMBUS_BLOCK_MAX && (tmp & DW_IC_DATA_CMD_DAT) > 0) {
- len = i2c_dw_recv_len(dev, tmp);
+ if (flags & I2C_M_RECV_LEN) {
+ if ((tmp <= I2C_SMBUS_BLOCK_MAX) && (tmp != 0))
+ len = i2c_dw_recv_len(dev, tmp);
+ else
+ i2c_dw_abort(dev);
}
+
*buf++ = tmp;
dev->rx_outstanding--;
}
--
2.17.1


2023-08-11 14:20:59

by Andy Shevchenko

[permalink] [raw]
Subject: Re: [PATCH 1/2] i2c: designware: fix __i2c_dw_disable in case master is holding SCL low

On Fri, Aug 11, 2023 at 02:46:23PM +0200, Yann Sionneau wrote:
> From: Yann Sionneau <[email protected]>
>
> The designware IP can be synthesized with the IC_EMPTYFIFO_HOLD_MASTER_EN

DesignWare

> parameter.
> In which case, if the TX FIFO gets empty and the last command didn't have

"In this case when the..."

> the STOP bit (IC_DATA_CMD[9]), the dw_apb_i2c will hold SCL low until

"the controller will..."

> a new command is pushed into the TX FIFO or the transfer is aborted.
>
> When the dw_apb_i2c is holding SCL low, it cannot be disabled.

"When the controller..."

> The transfer must first be aborted.
> Also, the bus recover won't work because SCL is held low by the master.
>
> This patch checks if the master is holding SCL low in __i2c_dw_disable

Grep for "This patch" in the Submitting Patches document and fix this
accordingly.

__i2c_dw_disable()

> before trying to disable the IP.
> If SCL is held low, an abort is initiated.
> When the abort is done, the disabling can then proceed.
>
> This whole situation can happen for instance during SMBUS read data block
> if the slave just responds with "byte count == 0".
> This puts the master in an unrecoverable state, holding SCL low and the
> current __i2c_dw_disable procedure is not working. In this situation

__i2c_dw_disable()

> only a Linux reboot can fix the i2c bus.

If reboot helps, what magic does it do that Linux OS can't repeat in software?
Please, elaborate more.

...

> int timeout = 100;
> u32 status;
> + u32 raw_intr_stats;
> + u32 enable;
> + bool abort_needed;
> + bool abort_done = false;

Perhaps reversed xmas tree order?

bool abort_done = false;
bool abort_needed;
u32 raw_intr_stats;
int timeout = 100;
u32 status;
u32 enable;

...

> + abort_needed = raw_intr_stats & DW_IC_INTR_MST_ON_HOLD;
> + if (abort_needed)
> + regmap_write(dev->map, DW_IC_ENABLE, enable | DW_IC_ENABLE_ABORT);
>
> do {
> + if (abort_needed && !abort_done) {
> + regmap_read(dev->map, DW_IC_ENABLE, &enable);
> + abort_done = !(enable & DW_IC_ENABLE_ABORT);
> + continue;

This will exhaust the timeout and below can be run at most once,
is it a problem?

Also it's a tight busyloop, are you sure it's what you need?

> + }

--
With Best Regards,
Andy Shevchenko



2023-08-11 14:23:04

by Andy Shevchenko

[permalink] [raw]
Subject: Re: [PATCH 2/2] i2c: designware: abort the transfer if receiving byte count of 0

On Fri, Aug 11, 2023 at 02:46:24PM +0200, Yann Sionneau wrote:
> From: Yann Sionneau <[email protected]>
>
> Context:
> It's not clear whether Linux SMBus stack supports receiving 0
> as byte count for SMBus read data block.
>
> Linux supports SMBus v2.0 spec, which says "The byte count may not be 0."
> Which does not seem very clear to me, as a non-native speaker.
> (Note that v3.0 of the spec says "The byte count may be 0.")
>
> Some drivers explicitly return -EPROTO in case of byte count 0.
>
> The issue:
> Regardless of whether Linux supports byte count of 0, if this happens
> the i2c-designware driver goes into an unrecoverable state holding
> SCL low if the IP is synthesized with the IC_EMPTYFIFO_HOLD_MASTER_EN
> parameter.
>
> The fix proposed by this patch:
> Abort the transfer by sending a STOP condition on the bus.
>
> Another approach would be to ignore the issue and let the driver
> timeout and disable the IP. The IP disabling is fixed by the previous
> patch in this patch series.
> The current patch just makes the recovery faster since Abort is sent
> directly without waiting for the timeout to happen. With this patch,
> disabling the IP is not necessary anymore.

...

> + if ((tmp <= I2C_SMBUS_BLOCK_MAX) && (tmp != 0))

if (tmp && tmp <= I2C_SMBUS_BLOCK_MAX)

> + len = i2c_dw_recv_len(dev, tmp);
> + else
> + i2c_dw_abort(dev);

--
With Best Regards,
Andy Shevchenko