All of the nodes under soc already have existing labels so use those
instead.
Signed-off-by: Robert Marko <[email protected]>
---
.../boot/dts/qcom/qcom-ipq4019-ap.dk01.1.dtsi | 140 +++++++++---------
1 file changed, 69 insertions(+), 71 deletions(-)
diff --git a/arch/arm/boot/dts/qcom/qcom-ipq4019-ap.dk01.1.dtsi b/arch/arm/boot/dts/qcom/qcom-ipq4019-ap.dk01.1.dtsi
index 0505270cf508..0714616c9e45 100644
--- a/arch/arm/boot/dts/qcom/qcom-ipq4019-ap.dk01.1.dtsi
+++ b/arch/arm/boot/dts/qcom/qcom-ipq4019-ap.dk01.1.dtsi
@@ -27,87 +27,85 @@ aliases {
chosen {
stdout-path = "serial0:115200n8";
};
+};
- soc {
- rng@22000 {
- status = "okay";
- };
+&prng {
+ status = "okay";
+};
- pinctrl@1000000 {
- serial_pins: serial_pinmux {
- mux {
- pins = "gpio60", "gpio61";
- function = "blsp_uart0";
- bias-disable;
- };
- };
-
- spi_0_pins: spi_0_pinmux {
- pinmux {
- function = "blsp_spi0";
- pins = "gpio55", "gpio56", "gpio57";
- };
- pinmux_cs {
- function = "gpio";
- pins = "gpio54";
- };
- pinconf {
- pins = "gpio55", "gpio56", "gpio57";
- drive-strength = <12>;
- bias-disable;
- };
- pinconf_cs {
- pins = "gpio54";
- drive-strength = <2>;
- bias-disable;
- output-high;
- };
- };
+&tlmm {
+ serial_pins: serial_pinmux {
+ mux {
+ pins = "gpio60", "gpio61";
+ function = "blsp_uart0";
+ bias-disable;
};
+ };
- blsp_dma: dma-controller@7884000 {
- status = "okay";
+ spi_0_pins: spi_0_pinmux {
+ pinmux {
+ function = "blsp_spi0";
+ pins = "gpio55", "gpio56", "gpio57";
};
-
- spi@78b5000 {
- pinctrl-0 = <&spi_0_pins>;
- pinctrl-names = "default";
- status = "okay";
- cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>;
-
- mx25l25635e@0 {
- #address-cells = <1>;
- #size-cells = <1>;
- reg = <0>;
- compatible = "mx25l25635e";
- spi-max-frequency = <24000000>;
- };
+ pinmux_cs {
+ function = "gpio";
+ pins = "gpio54";
};
-
- serial@78af000 {
- pinctrl-0 = <&serial_pins>;
- pinctrl-names = "default";
- status = "okay";
+ pinconf {
+ pins = "gpio55", "gpio56", "gpio57";
+ drive-strength = <12>;
+ bias-disable;
};
-
- cryptobam: dma-controller@8e04000 {
- status = "okay";
+ pinconf_cs {
+ pins = "gpio54";
+ drive-strength = <2>;
+ bias-disable;
+ output-high;
};
+ };
+};
- crypto@8e3a000 {
- status = "okay";
- };
+&blsp_dma {
+ status = "okay";
+};
- watchdog@b017000 {
- status = "okay";
- };
+&blsp1_spi1 {
+ pinctrl-0 = <&spi_0_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+ cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>;
+
+ mx25l25635e@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0>;
+ compatible = "mx25l25635e";
+ spi-max-frequency = <24000000>;
+ };
+};
- wifi@a000000 {
- status = "okay";
- };
+&blsp1_uart1 {
+ pinctrl-0 = <&serial_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
- wifi@a800000 {
- status = "okay";
- };
- };
+&cryptobam {
+ status = "okay";
+};
+
+&crypto {
+ status = "okay";
+};
+
+&watchdog {
+ status = "okay";
+};
+
+&wifi0 {
+ status = "okay";
+};
+
+&wifi1 {
+ status = "okay";
};
--
2.41.0
On Fri, 11 Aug 2023 at 23:27, Konrad Dybcio <[email protected]> wrote:
>
> On 11.08.2023 23:01, Robert Marko wrote:
> > All of the nodes under soc already have existing labels so use those
> > instead.
> >
> > Signed-off-by: Robert Marko <[email protected]>
> > ---
> dtx_diff returns an empty diff, nice
>
> Reviewed-by: Konrad Dybcio <[email protected]>
>
> Couple further suggestions:
>
> - wdog can probably enabled unconditionally
> - same for blsp dma since there's only one host so it must be
> used by something
> - same for crypto engine as it's a common piece of hw
> - you can drop mux{}, pinmux{}, pinconf{} from pin nodes, just add
> the properties directly under the pin nodes
> - this devicetree could use some schema warnings cleanup (make dtbs_check
> plus things like no underscores in node names)
Hi,
Yeah, I am planning a follow-up to clean up the pinctrl and most of
the stuff you mentioned
for the SoC DTSI itself.
I wanted to keep the diff clean here and just use the labels.
Regards,
Robert
>
> Konrad
> > .../boot/dts/qcom/qcom-ipq4019-ap.dk01.1.dtsi | 140 +++++++++---------
> > 1 file changed, 69 insertions(+), 71 deletions(-)
> >
> > diff --git a/arch/arm/boot/dts/qcom/qcom-ipq4019-ap.dk01.1.dtsi b/arch/arm/boot/dts/qcom/qcom-ipq4019-ap.dk01.1.dtsi
> > index 0505270cf508..0714616c9e45 100644
> > --- a/arch/arm/boot/dts/qcom/qcom-ipq4019-ap.dk01.1.dtsi
> > +++ b/arch/arm/boot/dts/qcom/qcom-ipq4019-ap.dk01.1.dtsi
> > @@ -27,87 +27,85 @@ aliases {
> > chosen {
> > stdout-path = "serial0:115200n8";
> > };
> > +};
> >
> > - soc {
> > - rng@22000 {
> > - status = "okay";
> > - };
> > +&prng {
> > + status = "okay";
> > +};
> >
> > - pinctrl@1000000 {
> > - serial_pins: serial_pinmux {
> > - mux {
> > - pins = "gpio60", "gpio61";
> > - function = "blsp_uart0";
> > - bias-disable;
> > - };
> > - };
> > -
> > - spi_0_pins: spi_0_pinmux {
> > - pinmux {
> > - function = "blsp_spi0";
> > - pins = "gpio55", "gpio56", "gpio57";
> > - };
> > - pinmux_cs {
> > - function = "gpio";
> > - pins = "gpio54";
> > - };
> > - pinconf {
> > - pins = "gpio55", "gpio56", "gpio57";
> > - drive-strength = <12>;
> > - bias-disable;
> > - };
> > - pinconf_cs {
> > - pins = "gpio54";
> > - drive-strength = <2>;
> > - bias-disable;
> > - output-high;
> > - };
> > - };
> > +&tlmm {
> > + serial_pins: serial_pinmux {
> > + mux {
> > + pins = "gpio60", "gpio61";
> > + function = "blsp_uart0";
> > + bias-disable;
> > };
> > + };
> >
> > - blsp_dma: dma-controller@7884000 {
> > - status = "okay";
> > + spi_0_pins: spi_0_pinmux {
> > + pinmux {
> > + function = "blsp_spi0";
> > + pins = "gpio55", "gpio56", "gpio57";
> > };
> > -
> > - spi@78b5000 {
> > - pinctrl-0 = <&spi_0_pins>;
> > - pinctrl-names = "default";
> > - status = "okay";
> > - cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>;
> > -
> > - mx25l25635e@0 {
> > - #address-cells = <1>;
> > - #size-cells = <1>;
> > - reg = <0>;
> > - compatible = "mx25l25635e";
> > - spi-max-frequency = <24000000>;
> > - };
> > + pinmux_cs {
> > + function = "gpio";
> > + pins = "gpio54";
> > };
> > -
> > - serial@78af000 {
> > - pinctrl-0 = <&serial_pins>;
> > - pinctrl-names = "default";
> > - status = "okay";
> > + pinconf {
> > + pins = "gpio55", "gpio56", "gpio57";
> > + drive-strength = <12>;
> > + bias-disable;
> > };
> > -
> > - cryptobam: dma-controller@8e04000 {
> > - status = "okay";
> > + pinconf_cs {
> > + pins = "gpio54";
> > + drive-strength = <2>;
> > + bias-disable;
> > + output-high;
> > };
> > + };
> > +};
> >
> > - crypto@8e3a000 {
> > - status = "okay";
> > - };
> > +&blsp_dma {
> > + status = "okay";
> > +};
> >
> > - watchdog@b017000 {
> > - status = "okay";
> > - };
> > +&blsp1_spi1 {
> > + pinctrl-0 = <&spi_0_pins>;
> > + pinctrl-names = "default";
> > + status = "okay";
> > + cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>;
> > +
> > + mx25l25635e@0 {
> > + #address-cells = <1>;
> > + #size-cells = <1>;
> > + reg = <0>;
> > + compatible = "mx25l25635e";
> > + spi-max-frequency = <24000000>;
> > + };
> > +};
> >
> > - wifi@a000000 {
> > - status = "okay";
> > - };
> > +&blsp1_uart1 {
> > + pinctrl-0 = <&serial_pins>;
> > + pinctrl-names = "default";
> > + status = "okay";
> > +};
> >
> > - wifi@a800000 {
> > - status = "okay";
> > - };
> > - };
> > +&cryptobam {
> > + status = "okay";
> > +};
> > +
> > +&crypto {
> > + status = "okay";
> > +};
> > +
> > +&watchdog {
> > + status = "okay";
> > +};
> > +
> > +&wifi0 {
> > + status = "okay";
> > +};
> > +
> > +&wifi1 {
> > + status = "okay";
> > };
On 11.08.2023 23:01, Robert Marko wrote:
> All of the nodes under soc already have existing labels so use those
> instead.
>
> Signed-off-by: Robert Marko <[email protected]>
> ---
dtx_diff returns an empty diff, nice
Reviewed-by: Konrad Dybcio <[email protected]>
Couple further suggestions:
- wdog can probably enabled unconditionally
- same for blsp dma since there's only one host so it must be
used by something
- same for crypto engine as it's a common piece of hw
- you can drop mux{}, pinmux{}, pinconf{} from pin nodes, just add
the properties directly under the pin nodes
- this devicetree could use some schema warnings cleanup (make dtbs_check
plus things like no underscores in node names)
Konrad
> .../boot/dts/qcom/qcom-ipq4019-ap.dk01.1.dtsi | 140 +++++++++---------
> 1 file changed, 69 insertions(+), 71 deletions(-)
>
> diff --git a/arch/arm/boot/dts/qcom/qcom-ipq4019-ap.dk01.1.dtsi b/arch/arm/boot/dts/qcom/qcom-ipq4019-ap.dk01.1.dtsi
> index 0505270cf508..0714616c9e45 100644
> --- a/arch/arm/boot/dts/qcom/qcom-ipq4019-ap.dk01.1.dtsi
> +++ b/arch/arm/boot/dts/qcom/qcom-ipq4019-ap.dk01.1.dtsi
> @@ -27,87 +27,85 @@ aliases {
> chosen {
> stdout-path = "serial0:115200n8";
> };
> +};
>
> - soc {
> - rng@22000 {
> - status = "okay";
> - };
> +&prng {
> + status = "okay";
> +};
>
> - pinctrl@1000000 {
> - serial_pins: serial_pinmux {
> - mux {
> - pins = "gpio60", "gpio61";
> - function = "blsp_uart0";
> - bias-disable;
> - };
> - };
> -
> - spi_0_pins: spi_0_pinmux {
> - pinmux {
> - function = "blsp_spi0";
> - pins = "gpio55", "gpio56", "gpio57";
> - };
> - pinmux_cs {
> - function = "gpio";
> - pins = "gpio54";
> - };
> - pinconf {
> - pins = "gpio55", "gpio56", "gpio57";
> - drive-strength = <12>;
> - bias-disable;
> - };
> - pinconf_cs {
> - pins = "gpio54";
> - drive-strength = <2>;
> - bias-disable;
> - output-high;
> - };
> - };
> +&tlmm {
> + serial_pins: serial_pinmux {
> + mux {
> + pins = "gpio60", "gpio61";
> + function = "blsp_uart0";
> + bias-disable;
> };
> + };
>
> - blsp_dma: dma-controller@7884000 {
> - status = "okay";
> + spi_0_pins: spi_0_pinmux {
> + pinmux {
> + function = "blsp_spi0";
> + pins = "gpio55", "gpio56", "gpio57";
> };
> -
> - spi@78b5000 {
> - pinctrl-0 = <&spi_0_pins>;
> - pinctrl-names = "default";
> - status = "okay";
> - cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>;
> -
> - mx25l25635e@0 {
> - #address-cells = <1>;
> - #size-cells = <1>;
> - reg = <0>;
> - compatible = "mx25l25635e";
> - spi-max-frequency = <24000000>;
> - };
> + pinmux_cs {
> + function = "gpio";
> + pins = "gpio54";
> };
> -
> - serial@78af000 {
> - pinctrl-0 = <&serial_pins>;
> - pinctrl-names = "default";
> - status = "okay";
> + pinconf {
> + pins = "gpio55", "gpio56", "gpio57";
> + drive-strength = <12>;
> + bias-disable;
> };
> -
> - cryptobam: dma-controller@8e04000 {
> - status = "okay";
> + pinconf_cs {
> + pins = "gpio54";
> + drive-strength = <2>;
> + bias-disable;
> + output-high;
> };
> + };
> +};
>
> - crypto@8e3a000 {
> - status = "okay";
> - };
> +&blsp_dma {
> + status = "okay";
> +};
>
> - watchdog@b017000 {
> - status = "okay";
> - };
> +&blsp1_spi1 {
> + pinctrl-0 = <&spi_0_pins>;
> + pinctrl-names = "default";
> + status = "okay";
> + cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>;
> +
> + mx25l25635e@0 {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + reg = <0>;
> + compatible = "mx25l25635e";
> + spi-max-frequency = <24000000>;
> + };
> +};
>
> - wifi@a000000 {
> - status = "okay";
> - };
> +&blsp1_uart1 {
> + pinctrl-0 = <&serial_pins>;
> + pinctrl-names = "default";
> + status = "okay";
> +};
>
> - wifi@a800000 {
> - status = "okay";
> - };
> - };
> +&cryptobam {
> + status = "okay";
> +};
> +
> +&crypto {
> + status = "okay";
> +};
> +
> +&watchdog {
> + status = "okay";
> +};
> +
> +&wifi0 {
> + status = "okay";
> +};
> +
> +&wifi1 {
> + status = "okay";
> };
Rename the SPI-NOR node to flash@0, remove #address-cells and #size-cells
as they should be under the partitions subnode and use the generic
jedec,spi-nor compatible.
Signed-off-by: Robert Marko <[email protected]>
---
arch/arm/boot/dts/qcom/qcom-ipq4019-ap.dk01.1.dtsi | 6 ++----
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/arch/arm/boot/dts/qcom/qcom-ipq4019-ap.dk01.1.dtsi b/arch/arm/boot/dts/qcom/qcom-ipq4019-ap.dk01.1.dtsi
index 0714616c9e45..f7ac8f9d0b6f 100644
--- a/arch/arm/boot/dts/qcom/qcom-ipq4019-ap.dk01.1.dtsi
+++ b/arch/arm/boot/dts/qcom/qcom-ipq4019-ap.dk01.1.dtsi
@@ -75,11 +75,9 @@ &blsp1_spi1 {
status = "okay";
cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>;
- mx25l25635e@0 {
- #address-cells = <1>;
- #size-cells = <1>;
+ flash@0 {
reg = <0>;
- compatible = "mx25l25635e";
+ compatible = "jedec,spi-nor";
spi-max-frequency = <24000000>;
};
};
--
2.41.0
On 12.08.2023 16:12, Robert Marko wrote:
> On Sat, 12 Aug 2023 at 16:08, Konrad Dybcio <[email protected]> wrote:
>>
>> On 12.08.2023 16:07, Robert Marko wrote:
>>> On Sat, 12 Aug 2023 at 12:47, Konrad Dybcio <[email protected]> wrote:
>>>>
>>>> On 12.08.2023 11:55, Robert Marko wrote:
>>>>> On Sat, 12 Aug 2023 at 00:56, Konrad Dybcio <[email protected]> wrote:
>>>>>>
>>>>>> On 11.08.2023 23:35, Robert Marko wrote:
>>>>>>> On Fri, 11 Aug 2023 at 23:28, Konrad Dybcio <[email protected]> wrote:
>>>>>>>>
>>>>>>>> On 11.08.2023 23:01, Robert Marko wrote:
>>>>>>>>> Rename the SPI-NOR node to flash@0, remove #address-cells and #size-cells
>>>>>>>>> as they should be under the partitions subnode and use the generic
>>>>>>>>> jedec,spi-nor compatible.
>>>>>>>>>
>>>>>>>>> Signed-off-by: Robert Marko <[email protected]>
>>>>>>>>> ---
>>>>>>>> You can also do "nandmanufacturer,mx25l25635e", "jedec,spi-nor"
>>>>>>>
>>>>>>> Hi,
>>>>>>> I grepped the vendor U-Boot to make sure it's not being triggered off
>>>>>>> the mx25l25635e
>>>>>>> compatible but the only hit is the IC support itself.
>>>>>>> MX25L25635 was just the original NOR IC Qualcomm used on the board so
>>>>>>> to me it made
>>>>>>> most sense to just use the JEDEC compatible as NOR itself is JEDEC NOR
>>>>>>> compatible.
>>>>>> OK if dynamic identification works fine
>>>>>
>>>>> It should work fine, datasheet is clear that its JEDEC compatible.
>>>>> That being said, I dont actually have the board, just figured it was
>>>>> time for a cleanup as
>>>>> OpenWrt has been patching DK01 and DK04 for ages.
>>>> Hm. Do we know whether there are still users of this boards?
>>>
>>> I honestly doubt it as they have been broken in OpenWrt for years and
>>> nobody complained.
>>> So we are currently removing support for them, but I still wanted to
>>> at least fixup the DTS state
>>> upstream.
>>> These boards are not obtainable anymore.
>> I also noticed they were detached from the other snapdragons in u-boot
>> for no good reason (at first glance anyway).
>
> If you are talking about the mainline U-Boot then yeah, my basic port was done
> years ago and I knew way less about the SoC then now.
> Currently its on my TODO to merge them with Snapdragon and add some proper
> GPIO and pinctrl drivers as well as using the Linux DTS.
Take a look at this branch of mine [1], I already did some of that.
If you wish to upstream that, please coordinate with Caleb (+CC) who
may be interested in the same in parallel.
[1] https://github.com/konradybcio/u-boot/commits/konrad/rb1_forcepushing
Konrad
On Sat, 12 Aug 2023 at 16:15, Konrad Dybcio <[email protected]> wrote:
>
> On 12.08.2023 16:12, Robert Marko wrote:
> > On Sat, 12 Aug 2023 at 16:08, Konrad Dybcio <[email protected]> wrote:
> >>
> >> On 12.08.2023 16:07, Robert Marko wrote:
> >>> On Sat, 12 Aug 2023 at 12:47, Konrad Dybcio <[email protected]> wrote:
> >>>>
> >>>> On 12.08.2023 11:55, Robert Marko wrote:
> >>>>> On Sat, 12 Aug 2023 at 00:56, Konrad Dybcio <[email protected]> wrote:
> >>>>>>
> >>>>>> On 11.08.2023 23:35, Robert Marko wrote:
> >>>>>>> On Fri, 11 Aug 2023 at 23:28, Konrad Dybcio <[email protected]> wrote:
> >>>>>>>>
> >>>>>>>> On 11.08.2023 23:01, Robert Marko wrote:
> >>>>>>>>> Rename the SPI-NOR node to flash@0, remove #address-cells and #size-cells
> >>>>>>>>> as they should be under the partitions subnode and use the generic
> >>>>>>>>> jedec,spi-nor compatible.
> >>>>>>>>>
> >>>>>>>>> Signed-off-by: Robert Marko <[email protected]>
> >>>>>>>>> ---
> >>>>>>>> You can also do "nandmanufacturer,mx25l25635e", "jedec,spi-nor"
> >>>>>>>
> >>>>>>> Hi,
> >>>>>>> I grepped the vendor U-Boot to make sure it's not being triggered off
> >>>>>>> the mx25l25635e
> >>>>>>> compatible but the only hit is the IC support itself.
> >>>>>>> MX25L25635 was just the original NOR IC Qualcomm used on the board so
> >>>>>>> to me it made
> >>>>>>> most sense to just use the JEDEC compatible as NOR itself is JEDEC NOR
> >>>>>>> compatible.
> >>>>>> OK if dynamic identification works fine
> >>>>>
> >>>>> It should work fine, datasheet is clear that its JEDEC compatible.
> >>>>> That being said, I dont actually have the board, just figured it was
> >>>>> time for a cleanup as
> >>>>> OpenWrt has been patching DK01 and DK04 for ages.
> >>>> Hm. Do we know whether there are still users of this boards?
> >>>
> >>> I honestly doubt it as they have been broken in OpenWrt for years and
> >>> nobody complained.
> >>> So we are currently removing support for them, but I still wanted to
> >>> at least fixup the DTS state
> >>> upstream.
> >>> These boards are not obtainable anymore.
> >> I also noticed they were detached from the other snapdragons in u-boot
> >> for no good reason (at first glance anyway).
> >
> > If you are talking about the mainline U-Boot then yeah, my basic port was done
> > years ago and I knew way less about the SoC then now.
> > Currently its on my TODO to merge them with Snapdragon and add some proper
> > GPIO and pinctrl drivers as well as using the Linux DTS.
> Take a look at this branch of mine [1], I already did some of that.
>
> If you wish to upstream that, please coordinate with Caleb (+CC) who
> may be interested in the same in parallel.
>
> [1] https://github.com/konradybcio/u-boot/commits/konrad/rb1_forcepushing
That is great, though this is very low hanging fruit for me, I have
plenty more of IPQ807x
stuff that needs to make its way upstream.
Regards,
Robert
>
> Konrad
On Fri, 11 Aug 2023 23:01:02 +0200, Robert Marko wrote:
> All of the nodes under soc already have existing labels so use those
> instead.
>
>
Applied, thanks!
[1/2] ARM: dts: qcom: ipq4019-ap.dk01.1: use existing labels for nodes
commit: 54850df251cb88ba9a32b6371c8cd5908efa3ec6
[2/2] ARM: dts: qcom: ipq4019-ap.dk01.1: align flash node with bindings
commit: 111bc3710caa7e55bc0040ffa57cec83e09dac07
Best regards,
--
Bjorn Andersson <[email protected]>