2023-08-13 13:41:12

by Guiting Shen

Subject: [PATCH RESEND] ASoC: tlv320aic32x4: Fix the divide by zero

The value of register(NDAC,MDAC,NADC,MADC,BCLKN) maybe zero lead to
divide by zero in clk_aic32x4_div_recalc_rate().And the rate should be
divide by 128 if the value was zero in this function according to the
datasheet.

Add the macro AIC32X4_DIV_MAX to present the 128 and return 0 if failing
to read the value of register.

Signed-off-by: Guiting Shen <[email protected]>
---
sound/soc/codecs/tlv320aic32x4-clk.c | 16 +++++++++++-----
sound/soc/codecs/tlv320aic32x4.h | 5 +++--
2 files changed, 14 insertions(+), 7 deletions(-)

diff --git a/sound/soc/codecs/tlv320aic32x4-clk.c b/sound/soc/codecs/tlv320aic32x4-clk.c
index c116e82f712d..5c0a76a4a106 100644
--- a/sound/soc/codecs/tlv320aic32x4-clk.c
+++ b/sound/soc/codecs/tlv320aic32x4-clk.c
@@ -321,7 +321,7 @@ static int clk_aic32x4_div_set_rate(struct clk_hw *hw, unsigned long rate,
u8 divisor;

divisor = DIV_ROUND_UP(parent_rate, rate);
- if (divisor > 128)
+ if (divisor > AIC32X4_DIV_MAX)
return -EINVAL;

return regmap_update_bits(div->regmap, div->reg,
@@ -334,7 +334,7 @@ static int clk_aic32x4_div_determine_rate(struct clk_hw *hw,
unsigned long divisor;

divisor = DIV_ROUND_UP(req->best_parent_rate, req->rate);
- if (divisor > 128)
+ if (divisor > AIC32X4_DIV_MAX)
return -EINVAL;

req->rate = DIV_ROUND_UP(req->best_parent_rate, divisor);
@@ -345,12 +345,18 @@ static unsigned long clk_aic32x4_div_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
struct clk_aic32x4 *div = to_clk_aic32x4(hw);
-
unsigned int val;
+ int err;
+
+ err = regmap_read(div->regmap, div->reg, &val);
+ if (err)
+ return 0;

- regmap_read(div->regmap, div->reg, &val);
+ val &= AIC32X4_DIV_MASK;
+ if (!val)
+ val = AIC32X4_DIV_MAX;

- return DIV_ROUND_UP(parent_rate, val & AIC32X4_DIV_MASK);
+ return DIV_ROUND_UP(parent_rate, val);
}

static const struct clk_ops aic32x4_div_ops = {
diff --git a/sound/soc/codecs/tlv320aic32x4.h b/sound/soc/codecs/tlv320aic32x4.h
index 4de5bd9e8cc5..d6101ce73f80 100644
--- a/sound/soc/codecs/tlv320aic32x4.h
+++ b/sound/soc/codecs/tlv320aic32x4.h
@@ -223,8 +223,9 @@ int aic32x4_register_clocks(struct device *dev, const char *mclk_name);
#define AIC32X4_REFPOWERUP_120MS 0x07

/* Common mask and enable for all of the dividers */
-#define AIC32X4_DIVEN BIT(7)
-#define AIC32X4_DIV_MASK GENMASK(6, 0)
+#define AIC32X4_DIVEN BIT(7)
+#define AIC32X4_DIV_MASK GENMASK(6, 0)
+#define AIC32X4_DIV_MAX 128

/* Clock Limits */
#define AIC32X4_MAX_DOSR_FREQ 6200000
--
2.25.1

2023-08-15 10:09:30

by Mark Brown

Subject: Re: [PATCH RESEND] ASoC: tlv320aic32x4: Fix the divide by zero

On Sun, 13 Aug 2023 20:55:20 +0800, Guiting Shen wrote:
> The value of register(NDAC,MDAC,NADC,MADC,BCLKN) maybe zero lead to
> divide by zero in clk_aic32x4_div_recalc_rate().And the rate should be
> divide by 128 if the value was zero in this function according to the
> datasheet.
>
> Add the macro AIC32X4_DIV_MAX to present the 128 and return 0 if failing
> to read the value of register.
>
> [...]

Applied to

https://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound.git for-next

Thanks!

[1/1] ASoC: tlv320aic32x4: Fix the divide by zero
commit: 11e756cc85fac43e2025306ad6aea80114cc7e98

All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent to Linus during
the next merge window (or sooner if it is a bug fix), however if
problems are discovered then the patch may be dropped or reverted.

You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.

If any updates are required or you are submitting further changes they
should be sent as incremental updates against current git, existing
patches will not be replaced.

Please add any relevant lists and maintainers to the CCs when replying
to this mail.

Thanks,
Mark