2023-08-14 10:58:47

by Xingyu Wu

Subject: [PATCH v4 3/3] riscv: dts: jh7110: starfive: Add timer node

Add the timer node for the Starfive JH7110 SoC.

Signed-off-by: Xingyu Wu <[email protected]>
---
arch/riscv/boot/dts/starfive/jh7110.dtsi | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)

diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
index ec2e70011a73..84bb9717be13 100644
--- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
@@ -502,6 +502,26 @@ sysgpio: pinctrl@13040000 {
#gpio-cells = <2>;
};

+ timer@13050000 {
+ compatible = "starfive,jh7110-timer";
+ reg = <0x0 0x13050000 0x0 0x10000>;
+ interrupts = <69>, <70>, <71> ,<72>;
+ clocks = <&syscrg JH7110_SYSCLK_TIMER_APB>,
+ <&syscrg JH7110_SYSCLK_TIMER0>,
+ <&syscrg JH7110_SYSCLK_TIMER1>,
+ <&syscrg JH7110_SYSCLK_TIMER2>,
+ <&syscrg JH7110_SYSCLK_TIMER3>;
+ clock-names = "apb", "ch0", "ch1",
+ "ch2", "ch3";
+ resets = <&syscrg JH7110_SYSRST_TIMER_APB>,
+ <&syscrg JH7110_SYSRST_TIMER0>,
+ <&syscrg JH7110_SYSRST_TIMER1>,
+ <&syscrg JH7110_SYSRST_TIMER2>,
+ <&syscrg JH7110_SYSRST_TIMER3>;
+ reset-names = "apb", "ch0", "ch1",
+ "ch2", "ch3";
+ };
+
watchdog@13070000 {
compatible = "starfive,jh7110-wdt";
reg = <0x0 0x13070000 0x0 0x10000>;
--
2.25.1

2023-08-18 10:28:38

by Walker Chen

Subject: Re: [PATCH v4 3/3] riscv: dts: jh7110: starfive: Add timer node

On 2023/8/14 18:16, Xingyu Wu wrote:
> Add the timer node for the Starfive JH7110 SoC.
>
> Signed-off-by: Xingyu Wu <[email protected]>
> ---
> arch/riscv/boot/dts/starfive/jh7110.dtsi | 20 ++++++++++++++++++++
> 1 file changed, 20 insertions(+)
>
> diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
> index ec2e70011a73..84bb9717be13 100644
> --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
> +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
> @@ -502,6 +502,26 @@ sysgpio: pinctrl@13040000 {
> #gpio-cells = <2>;
> };
>
> + timer@13050000 {
> + compatible = "starfive,jh7110-timer";
> + reg = <0x0 0x13050000 0x0 0x10000>;
> + interrupts = <69>, <70>, <71> ,<72>;
> + clocks = <&syscrg JH7110_SYSCLK_TIMER_APB>,
> + <&syscrg JH7110_SYSCLK_TIMER0>,
> + <&syscrg JH7110_SYSCLK_TIMER1>,
> + <&syscrg JH7110_SYSCLK_TIMER2>,
> + <&syscrg JH7110_SYSCLK_TIMER3>;
> + clock-names = "apb", "ch0", "ch1",
> + "ch2", "ch3";
> + resets = <&syscrg JH7110_SYSRST_TIMER_APB>,
> + <&syscrg JH7110_SYSRST_TIMER0>,
> + <&syscrg JH7110_SYSRST_TIMER1>,
> + <&syscrg JH7110_SYSRST_TIMER2>,
> + <&syscrg JH7110_SYSRST_TIMER3>;
> + reset-names = "apb", "ch0", "ch1",
> + "ch2", "ch3";
> + };
> +
> watchdog@13070000 {
> compatible = "starfive,jh7110-wdt";
> reg = <0x0 0x13070000 0x0 0x10000>;

Reviewed-by: Walker Chen <[email protected]>
Thanks!