From: Jinrong Liang <[email protected]>
KVM user sapce may control the Intel guest PMU version number via
CPUID.0AH:EAX[07:00]. A test is added to check if a typical PMU register
that is not available at the current version number is leaking.
Co-developed-by: Like Xu <[email protected]>
Signed-off-by: Like Xu <[email protected]>
Signed-off-by: Jinrong Liang <[email protected]>
---
.../kvm/x86_64/pmu_basic_functionality_test.c | 67 +++++++++++++++++++
1 file changed, 67 insertions(+)
diff --git a/tools/testing/selftests/kvm/x86_64/pmu_basic_functionality_test.c b/tools/testing/selftests/kvm/x86_64/pmu_basic_functionality_test.c
index 3bbf3bd2846b..70adfad45010 100644
--- a/tools/testing/selftests/kvm/x86_64/pmu_basic_functionality_test.c
+++ b/tools/testing/selftests/kvm/x86_64/pmu_basic_functionality_test.c
@@ -16,6 +16,12 @@
/* Guest payload for any performance counter counting */
#define NUM_BRANCHES 10
+/*
+ * KVM implements the first two non-existent counters (MSR_P6_PERFCTRx)
+ * via kvm_pr_unimpl_wrmsr() instead of #GP.
+ */
+#define MSR_INTEL_ARCH_PMU_GPCTR (MSR_IA32_PERFCTR0 + 2)
+
static const uint64_t perf_caps[] = {
0,
PMU_CAP_FW_WRITES,
@@ -341,6 +347,66 @@ static void intel_test_fixed_counters(void)
}
}
+static void intel_guest_check_pmu_version(uint8_t version)
+{
+ switch (version) {
+ case 0:
+ GUEST_SYNC(wrmsr_safe(MSR_INTEL_ARCH_PMU_GPCTR, 0xffffull));
+ case 1:
+ GUEST_SYNC(wrmsr_safe(MSR_CORE_PERF_GLOBAL_CTRL, 0x1ull));
+ case 2:
+ /*
+ * AnyThread Bit is only supported in version 3
+ *
+ * The strange thing is that when version=0, writing ANY-Any
+ * Thread bit (bit 21) in MSR_P6_EVNTSEL0 and MSR_P6_EVNTSEL1
+ * will not generate #GP. While writing ANY-Any Thread bit
+ * (bit 21) in MSR_P6_EVNTSEL0+x (MAX_GP_CTR_NUM > x > 2) to
+ * ANY-Any Thread bit (bit 21) will generate #GP.
+ */
+ if (version == 0)
+ break;
+
+ GUEST_SYNC(wrmsr_safe(MSR_P6_EVNTSEL0,
+ ARCH_PERFMON_EVENTSEL_ANY));
+ break;
+ default:
+ /* KVM currently supports up to pmu version 2 */
+ GUEST_SYNC(GP_VECTOR);
+ }
+
+ GUEST_DONE();
+}
+
+static void test_pmu_version_setup(struct kvm_vcpu *vcpu, uint8_t version,
+ uint64_t expected)
+{
+ uint64_t msr_val = 0;
+
+ vcpu_set_cpuid_property(vcpu, X86_PROPERTY_PMU_VERSION, version);
+
+ vcpu_args_set(vcpu, 1, version);
+ while (run_vcpu(vcpu, &msr_val) != UCALL_DONE)
+ TEST_ASSERT_EQ(expected, msr_val);
+}
+
+static void intel_test_pmu_version(void)
+{
+ uint8_t unsupported_version = kvm_cpu_property(X86_PROPERTY_PMU_VERSION) + 1;
+ struct kvm_vcpu *vcpu;
+ struct kvm_vm *vm;
+ uint8_t version;
+
+ TEST_REQUIRE(kvm_cpu_property(X86_PROPERTY_PMU_NR_FIXED_COUNTERS) > 2);
+
+ for (version = 0; version <= unsupported_version; version++) {
+ vm = pmu_vm_create_with_one_vcpu(&vcpu,
+ intel_guest_check_pmu_version);
+ test_pmu_version_setup(vcpu, version, GP_VECTOR);
+ kvm_vm_free(vm);
+ }
+}
+
int main(int argc, char *argv[])
{
TEST_REQUIRE(get_kvm_param_bool("enable_pmu"));
@@ -353,6 +419,7 @@ int main(int argc, char *argv[])
intel_test_arch_events();
intel_test_counters_num();
intel_test_fixed_counters();
+ intel_test_pmu_version();
return 0;
}
--
2.39.3