On 01.09.2023 14:10:43, Srinivas Goud wrote:
> ECC feature added to Tx and Rx FIFOs for Xilinx AXI CAN Controller.
> Part of this feature configuration and counter registers added in
> IP for 1bit/2bit ECC errors.
>
> xlnx,has-ecc is optional property and added to Xilinx AXI CAN Controller
> node if ECC block enabled in the HW
>
> Signed-off-by: Srinivas Goud <[email protected]>
> ---
> Changes in v4:
> Fix binding check warning
> Update property description
>
> Changes in v3:
> Update commit description
>
> Changes in v2:
> None
>
> Documentation/devicetree/bindings/net/can/xilinx,can.yaml | 5 +++++
> 1 file changed, 5 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/net/can/xilinx,can.yaml b/Documentation/devicetree/bindings/net/can/xilinx,can.yaml
> index 64d57c3..50a2671 100644
> --- a/Documentation/devicetree/bindings/net/can/xilinx,can.yaml
> +++ b/Documentation/devicetree/bindings/net/can/xilinx,can.yaml
> @@ -49,6 +49,10 @@ properties:
> resets:
> maxItems: 1
>
> + xlnx,has-ecc:
> + $ref: /schemas/types.yaml#/definitions/flag
> + description: CAN Tx and Rx fifo has ECC (AXI CAN)
Are there 2 FIFOs? If so I'd phrase it this way:
"CAN TX and RX FIFOs have ECC support (AXI CAN)" - or -
"CAN TX and RX FIFOs support ECC"
Marc
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