2023-09-14 08:21:43

by Kathiravan Thirumoorthy

Subject: [PATCH v2 10/11] arm64: dts: qcom: ipq9574: include the GPLL0 as clock provider for mailbox

While the kernel is booting up, APSS PLL will be running at 800MHz with
GPLL0 as source. Once the cpufreq driver is available, APSS PLL will be
configured to the rate based on the opp table and the source also will
be changed to APSS_PLL_EARLY. So allow the mailbox to consume the GPLL0,
with this inclusion, CPU Freq correctly reports that CPU is running at
800MHz rather than 24MHz.

Signed-off-by: Kathiravan Thirumoorthy <[email protected]>
---
Changes in V2:
- Splitted the change into target specific file
---
arch/arm64/boot/dts/qcom/ipq9574.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
index 51aba071c1eb..89edb4b852df 100644
--- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
@@ -652,8 +652,8 @@ apcs_glb: mailbox@b111000 {
"qcom,ipq6018-apcs-apps-global";
reg = <0x0b111000 0x1000>;
#clock-cells = <1>;
- clocks = <&a73pll>, <&xo_board_clk>;
- clock-names = "pll", "xo";
+ clocks = <&a73pll>, <&xo_board_clk>, <&gcc GPLL0>;
+ clock-names = "pll", "xo", "gpll0";
#mbox-cells = <1>;
};


--
2.34.1

2023-09-27 11:51:25

by Konrad Dybcio

Subject: Re: [PATCH v2 10/11] arm64: dts: qcom: ipq9574: include the GPLL0 as clock provider for mailbox

On 14.09.2023 09:00, Kathiravan Thirumoorthy wrote:
> While the kernel is booting up, APSS PLL will be running at 800MHz with
> GPLL0 as source. Once the cpufreq driver is available, APSS PLL will be
> configured to the rate based on the opp table and the source also will
> be changed to APSS_PLL_EARLY. So allow the mailbox to consume the GPLL0,
> with this inclusion, CPU Freq correctly reports that CPU is running at
> 800MHz rather than 24MHz.
>
> Signed-off-by: Kathiravan Thirumoorthy <[email protected]>
> ---
Reviewed-by: Konrad Dybcio <[email protected]>

Konrad