2023-09-13 03:19:48

by Joshua Yeong

Subject: [PATCH v2 0/1] Cadence I3C Status Register Bit Mask Error

I3C ibirfifodepth and cmdrfifodepth field should read from status0 instead of
status1. Update I3C slave macro.

Joshua Yeong (1):
i3c: master: cdns: Fix reading status register

drivers/i3c/master/i3c-master-cdns.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)

--
2.25.1

2023-09-13 03:20:14

by Joshua Yeong

Subject: [PATCH v2 1/1] i3c: master: cdns: Fix reading status register

IBIR_DEPTH and CMDR_DEPTH should read from status0 instead of status1.

Cc: [email protected]
Fixes: 603f2bee2c54 ("i3c: master: Add driver for Cadence IP")
Signed-off-by: Joshua Yeong <[email protected]>
---
drivers/i3c/master/i3c-master-cdns.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/i3c/master/i3c-master-cdns.c b/drivers/i3c/master/i3c-master-cdns.c
index 49551db71bc9..8f1fda3c7ac5 100644
--- a/drivers/i3c/master/i3c-master-cdns.c
+++ b/drivers/i3c/master/i3c-master-cdns.c
@@ -191,7 +191,7 @@
#define SLV_STATUS1_HJ_DIS BIT(18)
#define SLV_STATUS1_MR_DIS BIT(17)
#define SLV_STATUS1_PROT_ERR BIT(16)
-#define SLV_STATUS1_DA(x) (((s) & GENMASK(15, 9)) >> 9)
+#define SLV_STATUS1_DA(s) (((s) & GENMASK(15, 9)) >> 9)
#define SLV_STATUS1_HAS_DA BIT(8)
#define SLV_STATUS1_DDR_RX_FULL BIT(7)
#define SLV_STATUS1_DDR_TX_FULL BIT(6)
@@ -1623,13 +1623,13 @@ static int cdns_i3c_master_probe(struct platform_device *pdev)
/* Device ID0 is reserved to describe this master. */
master->maxdevs = CONF_STATUS0_DEVS_NUM(val);
master->free_rr_slots = GENMASK(master->maxdevs, 1);
+ master->caps.ibirfifodepth = CONF_STATUS0_IBIR_DEPTH(val);
+ master->caps.cmdrfifodepth = CONF_STATUS0_CMDR_DEPTH(val);

val = readl(master->regs + CONF_STATUS1);
master->caps.cmdfifodepth = CONF_STATUS1_CMD_DEPTH(val);
master->caps.rxfifodepth = CONF_STATUS1_RX_DEPTH(val);
master->caps.txfifodepth = CONF_STATUS1_TX_DEPTH(val);
- master->caps.ibirfifodepth = CONF_STATUS0_IBIR_DEPTH(val);
- master->caps.cmdrfifodepth = CONF_STATUS0_CMDR_DEPTH(val);

spin_lock_init(&master->ibi.lock);
master->ibi.num_slots = CONF_STATUS1_IBI_HW_RES(val);
--
2.25.1

2023-09-14 02:01:36

by Miquel Raynal

Subject: Re: [PATCH v2 1/1] i3c: master: cdns: Fix reading status register

Hi Joshua,

[email protected] wrote on Wed, 13 Sep 2023 11:17:45 +0800:

> IBIR_DEPTH and CMDR_DEPTH should read from status0 instead of status1.
>
> Cc: [email protected]
> Fixes: 603f2bee2c54 ("i3c: master: Add driver for Cadence IP")
> Signed-off-by: Joshua Yeong <[email protected]>

Reviewed-by: Miquel Raynal <[email protected]>

Thanks,
Miquèl

2023-09-26 01:51:16

by Alexandre Belloni

Subject: Re: [PATCH v2 0/1] Cadence I3C Status Register Bit Mask Error

On Wed, 13 Sep 2023 11:17:43 +0800, Joshua Yeong wrote:
> I3C ibirfifodepth and cmdrfifodepth field should read from status0 instead of
> status1. Update I3C slave macro.
>
> Joshua Yeong (1):
> i3c: master: cdns: Fix reading status register
>
> drivers/i3c/master/i3c-master-cdns.c | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
> [...]

Applied, thanks!

[1/1] i3c: master: cdns: Fix reading status register
commit: 4bd8405257da717cd556f99e5fb68693d12c9766

Best regards,

--
Alexandre Belloni, co-owner and COO, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com