I noticed that we've added HWCAP2_HBC without updating the
documentation, and in the process also noticed that some user visible
fields in ID_AA64ISAR2_EL1 are not documented. Fix these issues.
Given the lack of any automatic generation or auditing there's almost
certainly more fields that are broken in cpu-feature-registers.rst, I
didn't check any other registers.
Signed-off-by: Mark Brown <[email protected]>
---
Mark Brown (2):
arm64/hbc: Document HWCAP2_HBC
arm64: Document missing userspace visible fields in ID_AA64ISAR2_EL1
Documentation/arch/arm64/cpu-feature-registers.rst | 10 ++++++++++
Documentation/arch/arm64/elf_hwcaps.rst | 3 +++
2 files changed, 13 insertions(+)
---
base-commit: 0bb80ecc33a8fb5a682236443c1e740d5c917d1d
change-id: 20230913-arm64-feat-hbc-doc-08e3d1741fdb
Best regards,
--
Mark Brown <[email protected]>
When we added support for FEAT_HBC we added a new hwcap but did not
document that we had done so, add the documentation.
Signed-off-by: Mark Brown <[email protected]>
---
Documentation/arch/arm64/elf_hwcaps.rst | 3 +++
1 file changed, 3 insertions(+)
diff --git a/Documentation/arch/arm64/elf_hwcaps.rst b/Documentation/arch/arm64/elf_hwcaps.rst
index 8c8addb4194c..76ff9d7398fd 100644
--- a/Documentation/arch/arm64/elf_hwcaps.rst
+++ b/Documentation/arch/arm64/elf_hwcaps.rst
@@ -305,6 +305,9 @@ HWCAP2_SMEF16F16
HWCAP2_MOPS
Functionality implied by ID_AA64ISAR2_EL1.MOPS == 0b0001.
+HWCAP2_HBC
+ Functionality implied by ID_AA64ISAR2_EL1.BC == 0b0001.
+
4. Unused AT_HWCAP bits
-----------------------
--
2.30.2
We have exposed a number of fields in ID_AA64ISAR2_EL1 to usersapce without
adding the matching documentation in cpu-feature-registers.rst, update it
to match the implementation.
Signed-off-by: Mark Brown <[email protected]>
---
Documentation/arch/arm64/cpu-feature-registers.rst | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/Documentation/arch/arm64/cpu-feature-registers.rst b/Documentation/arch/arm64/cpu-feature-registers.rst
index 4e4625f2455f..46fd82acafab 100644
--- a/Documentation/arch/arm64/cpu-feature-registers.rst
+++ b/Documentation/arch/arm64/cpu-feature-registers.rst
@@ -288,8 +288,18 @@ infrastructure:
+------------------------------+---------+---------+
| Name | bits | visible |
+------------------------------+---------+---------+
+ | CSSC | [55-52] | y |
+ +------------------------------+---------+---------+
+ | RPRFM | [51-48] | y |
+ +------------------------------+---------+---------+
+ | BC | [23-20] | y |
+ +------------------------------+---------+---------+
| MOPS | [19-16] | y |
+------------------------------+---------+---------+
+ | APA3 | [15-12] | y |
+ +------------------------------+---------+---------+
+ | GPA3 | [11-8] | y |
+ +------------------------------+---------+---------+
| RPRES | [7-4] | y |
+------------------------------+---------+---------+
| WFXT | [3-0] | y |
--
2.30.2
On Thu, Sep 14, 2023 at 11:09:28AM +0100, Mark Brown wrote:
> I noticed that we've added HWCAP2_HBC without updating the
> documentation, and in the process also noticed that some user visible
> fields in ID_AA64ISAR2_EL1 are not documented. Fix these issues.
>
> Given the lack of any automatic generation or auditing there's almost
> certainly more fields that are broken in cpu-feature-registers.rst, I
> didn't check any other registers.
>
> Signed-off-by: Mark Brown <[email protected]>
> ---
> Mark Brown (2):
> arm64/hbc: Document HWCAP2_HBC
> arm64: Document missing userspace visible fields in ID_AA64ISAR2_EL1
>
> Documentation/arch/arm64/cpu-feature-registers.rst | 10 ++++++++++
> Documentation/arch/arm64/elf_hwcaps.rst | 3 +++
> 2 files changed, 13 insertions(+)
> ---
> base-commit: 0bb80ecc33a8fb5a682236443c1e740d5c917d1d
> change-id: 20230913-arm64-feat-hbc-doc-08e3d1741fdb
>
> Best regards,
> --
> Mark Brown <[email protected]>
>
I sent out a fix for this yesterday:
https://lore.kernel.org/linux-arm-kernel/[email protected]/T/#t
Kristina also noticed cpu-feature-registers.rst hadn't been updated either, so I was just about to
send out a v2 that matches your patches. I won't do that since you've just done it!
Reviewed-by: Joey Gouly <[email protected]>
Thanks,
Joey
On Thu, 14 Sep 2023 11:09:28 +0100, Mark Brown wrote:
> I noticed that we've added HWCAP2_HBC without updating the
> documentation, and in the process also noticed that some user visible
> fields in ID_AA64ISAR2_EL1 are not documented. Fix these issues.
>
> Given the lack of any automatic generation or auditing there's almost
> certainly more fields that are broken in cpu-feature-registers.rst, I
> didn't check any other registers.
>
> [...]
Applied to arm64 (for-next/fixes), thanks!
[1/2] arm64/hbc: Document HWCAP2_HBC
https://git.kernel.org/arm64/c/5ad361f42fe4
[2/2] arm64: Document missing userspace visible fields in ID_AA64ISAR2_EL1
https://git.kernel.org/arm64/c/44a5b6b5c7fe
Cheers,
--
Will
https://fixes.arm64.dev
https://next.arm64.dev
https://will.arm64.dev