From: Zelong Dong <[email protected]>
This patchset adds Reset controller driver support for Amlogic C3 SoC.
The RESET registers count and offset for C3 Soc are same as S4 Soc.
Changes since v1:
- remove Change-ID
- run scripts/checkpatch.pl and fix reported warnings
- sort dts node by base reg offset
Changes since v2:
- replace keyword "meson" with "amlogic"
Changes since v3:
- rebase on v6.6-rc1
---
v1:https://lore.kernel.org/all/[email protected]/
v2:https://lore.kernel.org/all/[email protected]/
v3:https://lore.kernel.org/all/[email protected]/
Zelong Dong (3):
dt-bindings: reset: Add compatible and DT bindings for Amlogic C3
Reset Controller
reset: reset-meson: add support for Amlogic C3 SoC Reset Controller
arm64: dts: amlogic: add reset controller for Amlogic C3 SoC
.../bindings/reset/amlogic,meson-reset.yaml | 1 +
arch/arm64/boot/dts/amlogic/amlogic-c3.dtsi | 7 ++
drivers/reset/reset-meson.c | 1 +
include/dt-bindings/reset/amlogic,c3-reset.h | 119 ++++++++++++++++++
4 files changed, 128 insertions(+)
create mode 100644 include/dt-bindings/reset/amlogic,c3-reset.h
--
2.35.1
From: Zelong Dong <[email protected]>
Add new compatible and DT bindings for Amlogic C3 Reset Controller
Signed-off-by: Zelong Dong <[email protected]>
Acked-by: Krzysztof Kozlowski <[email protected]>
Reviewed-by: Dmitry Rokosov <[email protected]>
Reviewed-by: Rob Herring <[email protected]>
---
.../bindings/reset/amlogic,meson-reset.yaml | 1 +
include/dt-bindings/reset/amlogic,c3-reset.h | 119 ++++++++++++++++++
2 files changed, 120 insertions(+)
create mode 100644 include/dt-bindings/reset/amlogic,c3-reset.h
diff --git a/Documentation/devicetree/bindings/reset/amlogic,meson-reset.yaml b/Documentation/devicetree/bindings/reset/amlogic,meson-reset.yaml
index d3fdee89d4f8..f0c6c0df0ce3 100644
--- a/Documentation/devicetree/bindings/reset/amlogic,meson-reset.yaml
+++ b/Documentation/devicetree/bindings/reset/amlogic,meson-reset.yaml
@@ -18,6 +18,7 @@ properties:
- amlogic,meson-axg-reset # Reset Controller on AXG and compatible SoCs
- amlogic,meson-a1-reset # Reset Controller on A1 and compatible SoCs
- amlogic,meson-s4-reset # Reset Controller on S4 and compatible SoCs
+ - amlogic,c3-reset # Reset Controller on C3 and compatible SoCs
reg:
maxItems: 1
diff --git a/include/dt-bindings/reset/amlogic,c3-reset.h b/include/dt-bindings/reset/amlogic,c3-reset.h
new file mode 100644
index 000000000000..d9127863f603
--- /dev/null
+++ b/include/dt-bindings/reset/amlogic,c3-reset.h
@@ -0,0 +1,119 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
+/*
+ * Copyright (c) 2023 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_AMLOGIC_C3_RESET_H
+#define _DT_BINDINGS_AMLOGIC_C3_RESET_H
+
+/* RESET0 */
+/* 0-3 */
+#define RESET_USBCTRL 4
+/* 5-7 */
+#define RESET_USBPHY20 8
+/* 9 */
+#define RESET_USB2DRD 10
+#define RESET_MIPI_DSI_HOST 11
+#define RESET_MIPI_DSI_PHY 12
+/* 13-20 */
+#define RESET_GE2D 21
+#define RESET_DWAP 22
+/* 23-31 */
+
+/* RESET1 */
+#define RESET_AUDIO 32
+/* 33-34 */
+#define RESET_DDRAPB 35
+#define RESET_DDR 36
+#define RESET_DOS_CAPB3 37
+#define RESET_DOS 38
+/* 39-46 */
+#define RESET_NNA 47
+#define RESET_ETHERNET 48
+#define RESET_ISP 49
+#define RESET_VC9000E_APB 50
+#define RESET_VC9000E_A 51
+/* 52 */
+#define RESET_VC9000E_CORE 53
+/* 54-63 */
+
+/* RESET2 */
+#define RESET_ABUS_ARB 64
+#define RESET_IRCTRL 65
+/* 66 */
+#define RESET_TEMP_PII 67
+/* 68-72 */
+#define RESET_SPICC_0 73
+#define RESET_SPICC_1 74
+#define RESET_RSA 75
+
+/* 76-79 */
+#define RESET_MSR_CLK 80
+#define RESET_SPIFC 81
+#define RESET_SAR_ADC 82
+/* 83-87 */
+#define RESET_ACODEC 88
+/* 89-90 */
+#define RESET_WATCHDOG 91
+/* 92-95 */
+
+/* RESET3 */
+#define RESET_ISP_NIC_GPV 96
+#define RESET_ISP_NIC_MAIN 97
+#define RESET_ISP_NIC_VCLK 98
+#define RESET_ISP_NIC_VOUT 99
+#define RESET_ISP_NIC_ALL 100
+#define RESET_VOUT 101
+#define RESET_VOUT_VENC 102
+/* 103 */
+#define RESET_CVE_NIC_GPV 104
+#define RESET_CVE_NIC_MAIN 105
+#define RESET_CVE_NIC_GE2D 106
+#define RESET_CVE_NIC_DW 106
+#define RESET_CVE_NIC_CVE 108
+#define RESET_CVE_NIC_ALL 109
+#define RESET_CVE 110
+/* 112-127 */
+
+/* RESET4 */
+#define RESET_RTC 128
+#define RESET_PWM_AB 129
+#define RESET_PWM_CD 130
+#define RESET_PWM_EF 131
+#define RESET_PWM_GH 132
+#define RESET_PWM_IJ 133
+#define RESET_PWM_KL 134
+#define RESET_PWM_MN 135
+/* 136-137 */
+#define RESET_UART_A 138
+#define RESET_UART_B 139
+#define RESET_UART_C 140
+#define RESET_UART_D 141
+#define RESET_UART_E 142
+#define RESET_UART_F 143
+#define RESET_I2C_S_A 144
+#define RESET_I2C_M_A 145
+#define RESET_I2C_M_B 146
+#define RESET_I2C_M_C 147
+#define RESET_I2C_M_D 148
+/* 149-151 */
+#define RESET_SD_EMMC_A 152
+#define RESET_SD_EMMC_B 153
+#define RESET_SD_EMMC_C 154
+
+/* RESET5 */
+/* 160-172 */
+#define RESET_BRG_NIC_NNA 173
+#define RESET_BRG_MUX_NIC_MAIN 174
+#define RESET_BRG_AO_NIC_ALL 175
+/* 176-183 */
+#define RESET_BRG_NIC_VAPB 184
+#define RESET_BRG_NIC_SDIO_B 185
+#define RESET_BRG_NIC_SDIO_A 186
+#define RESET_BRG_NIC_EMMC 187
+#define RESET_BRG_NIC_DSU 188
+#define RESET_BRG_NIC_SYSCLK 189
+#define RESET_BRG_NIC_MAIN 190
+#define RESET_BRG_NIC_ALL 191
+
+#endif
--
2.35.1
From: Zelong Dong <[email protected]>
Add a new compatible string to support for the reset controller
on the C3 SoC. The count and offset for C3 Soc RESET registers are
same as S4 Soc.
Signed-off-by: Zelong Dong <[email protected]>
Reviewed-by: Dmitry Rokosov <[email protected]>
Reviewed-by: Martin Blumenstingl <[email protected]>
---
drivers/reset/reset-meson.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/reset/reset-meson.c b/drivers/reset/reset-meson.c
index a7af051b17fb..f78be97898bc 100644
--- a/drivers/reset/reset-meson.c
+++ b/drivers/reset/reset-meson.c
@@ -108,6 +108,7 @@ static const struct of_device_id meson_reset_dt_ids[] = {
{ .compatible = "amlogic,meson-axg-reset", .data = &meson8b_param},
{ .compatible = "amlogic,meson-a1-reset", .data = &meson_a1_param},
{ .compatible = "amlogic,meson-s4-reset", .data = &meson_s4_param},
+ { .compatible = "amlogic,c3-reset", .data = &meson_s4_param},
{ /* sentinel */ },
};
MODULE_DEVICE_TABLE(of, meson_reset_dt_ids);
--
2.35.1
From: Zelong Dong <[email protected]>
Add the reset controller device of Amlogic C3 SoC family
Signed-off-by: Zelong Dong <[email protected]>
Reviewed-by: Dmitry Rokosov <[email protected]>
---
arch/arm64/boot/dts/amlogic/amlogic-c3.dtsi | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/amlogic-c3.dtsi b/arch/arm64/boot/dts/amlogic/amlogic-c3.dtsi
index 998f5050795c..d086bfab3228 100644
--- a/arch/arm64/boot/dts/amlogic/amlogic-c3.dtsi
+++ b/arch/arm64/boot/dts/amlogic/amlogic-c3.dtsi
@@ -6,6 +6,7 @@
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/reset/amlogic,c3-reset.h>
/ {
cpus {
@@ -81,6 +82,12 @@ apb4: bus@fe000000 {
#size-cells = <2>;
ranges = <0x0 0x0 0x0 0xfe000000 0x0 0x480000>;
+ reset: reset-controller@2000 {
+ compatible = "amlogic,c3-reset";
+ reg = <0x0 0x2000 0x0 0x98>;
+ #reset-cells = <1>;
+ };
+
periphs_pinctrl: pinctrl@4000 {
compatible = "amlogic,c3-periphs-pinctrl";
#address-cells = <2>;
--
2.35.1
On 14/09/2023 08:40, zelong dong wrote:
> From: Zelong Dong <[email protected]>
>
> Add a new compatible string to support for the reset controller
> on the C3 SoC. The count and offset for C3 Soc RESET registers are
> same as S4 Soc.
>
> Signed-off-by: Zelong Dong <[email protected]>
> Reviewed-by: Dmitry Rokosov <[email protected]>
> Reviewed-by: Martin Blumenstingl <[email protected]>
> ---
> drivers/reset/reset-meson.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/reset/reset-meson.c b/drivers/reset/reset-meson.c
> index a7af051b17fb..f78be97898bc 100644
> --- a/drivers/reset/reset-meson.c
> +++ b/drivers/reset/reset-meson.c
> @@ -108,6 +108,7 @@ static const struct of_device_id meson_reset_dt_ids[] = {
> { .compatible = "amlogic,meson-axg-reset", .data = &meson8b_param},
> { .compatible = "amlogic,meson-a1-reset", .data = &meson_a1_param},
> { .compatible = "amlogic,meson-s4-reset", .data = &meson_s4_param},
> + { .compatible = "amlogic,c3-reset", .data = &meson_s4_param},
> { /* sentinel */ },
> };
> MODULE_DEVICE_TABLE(of, meson_reset_dt_ids);
Reviewed-by: Neil Armstrong <[email protected]>
On 14/09/2023 08:40, zelong dong wrote:
> From: Zelong Dong <[email protected]>
>
> Add the reset controller device of Amlogic C3 SoC family
>
> Signed-off-by: Zelong Dong <[email protected]>
> Reviewed-by: Dmitry Rokosov <[email protected]>
> ---
> arch/arm64/boot/dts/amlogic/amlogic-c3.dtsi | 7 +++++++
> 1 file changed, 7 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/amlogic/amlogic-c3.dtsi b/arch/arm64/boot/dts/amlogic/amlogic-c3.dtsi
> index 998f5050795c..d086bfab3228 100644
> --- a/arch/arm64/boot/dts/amlogic/amlogic-c3.dtsi
> +++ b/arch/arm64/boot/dts/amlogic/amlogic-c3.dtsi
> @@ -6,6 +6,7 @@
> #include <dt-bindings/interrupt-controller/irq.h>
> #include <dt-bindings/interrupt-controller/arm-gic.h>
> #include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/reset/amlogic,c3-reset.h>
>
> / {
> cpus {
> @@ -81,6 +82,12 @@ apb4: bus@fe000000 {
> #size-cells = <2>;
> ranges = <0x0 0x0 0x0 0xfe000000 0x0 0x480000>;
>
> + reset: reset-controller@2000 {
> + compatible = "amlogic,c3-reset";
> + reg = <0x0 0x2000 0x0 0x98>;
> + #reset-cells = <1>;
> + };
> +
> periphs_pinctrl: pinctrl@4000 {
> compatible = "amlogic,c3-periphs-pinctrl";
> #address-cells = <2>;
Reviewed-by: Neil Armstrong <[email protected]>
On 14/09/2023 08:40, zelong dong wrote:
> From: Zelong Dong <[email protected]>
>
> Add new compatible and DT bindings for Amlogic C3 Reset Controller
>
> Signed-off-by: Zelong Dong <[email protected]>
> Acked-by: Krzysztof Kozlowski <[email protected]>
> Reviewed-by: Dmitry Rokosov <[email protected]>
> Reviewed-by: Rob Herring <[email protected]>
> ---
> .../bindings/reset/amlogic,meson-reset.yaml | 1 +
> include/dt-bindings/reset/amlogic,c3-reset.h | 119 ++++++++++++++++++
> 2 files changed, 120 insertions(+)
> create mode 100644 include/dt-bindings/reset/amlogic,c3-reset.h
>
> diff --git a/Documentation/devicetree/bindings/reset/amlogic,meson-reset.yaml b/Documentation/devicetree/bindings/reset/amlogic,meson-reset.yaml
> index d3fdee89d4f8..f0c6c0df0ce3 100644
> --- a/Documentation/devicetree/bindings/reset/amlogic,meson-reset.yaml
> +++ b/Documentation/devicetree/bindings/reset/amlogic,meson-reset.yaml
> @@ -18,6 +18,7 @@ properties:
> - amlogic,meson-axg-reset # Reset Controller on AXG and compatible SoCs
> - amlogic,meson-a1-reset # Reset Controller on A1 and compatible SoCs
> - amlogic,meson-s4-reset # Reset Controller on S4 and compatible SoCs
> + - amlogic,c3-reset # Reset Controller on C3 and compatible SoCs
>
> reg:
> maxItems: 1
> diff --git a/include/dt-bindings/reset/amlogic,c3-reset.h b/include/dt-bindings/reset/amlogic,c3-reset.h
> new file mode 100644
> index 000000000000..d9127863f603
> --- /dev/null
> +++ b/include/dt-bindings/reset/amlogic,c3-reset.h
> @@ -0,0 +1,119 @@
> +/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
> +/*
> + * Copyright (c) 2023 Amlogic, Inc. All rights reserved.
> + */
> +
> +#ifndef _DT_BINDINGS_AMLOGIC_C3_RESET_H
> +#define _DT_BINDINGS_AMLOGIC_C3_RESET_H
> +
> +/* RESET0 */
> +/* 0-3 */
> +#define RESET_USBCTRL 4
> +/* 5-7 */
> +#define RESET_USBPHY20 8
> +/* 9 */
> +#define RESET_USB2DRD 10
> +#define RESET_MIPI_DSI_HOST 11
> +#define RESET_MIPI_DSI_PHY 12
> +/* 13-20 */
> +#define RESET_GE2D 21
> +#define RESET_DWAP 22
> +/* 23-31 */
> +
> +/* RESET1 */
> +#define RESET_AUDIO 32
> +/* 33-34 */
> +#define RESET_DDRAPB 35
> +#define RESET_DDR 36
> +#define RESET_DOS_CAPB3 37
> +#define RESET_DOS 38
> +/* 39-46 */
> +#define RESET_NNA 47
> +#define RESET_ETHERNET 48
> +#define RESET_ISP 49
> +#define RESET_VC9000E_APB 50
> +#define RESET_VC9000E_A 51
> +/* 52 */
> +#define RESET_VC9000E_CORE 53
> +/* 54-63 */
> +
> +/* RESET2 */
> +#define RESET_ABUS_ARB 64
> +#define RESET_IRCTRL 65
> +/* 66 */
> +#define RESET_TEMP_PII 67
> +/* 68-72 */
> +#define RESET_SPICC_0 73
> +#define RESET_SPICC_1 74
> +#define RESET_RSA 75
> +
> +/* 76-79 */
> +#define RESET_MSR_CLK 80
> +#define RESET_SPIFC 81
> +#define RESET_SAR_ADC 82
> +/* 83-87 */
> +#define RESET_ACODEC 88
> +/* 89-90 */
> +#define RESET_WATCHDOG 91
> +/* 92-95 */
> +
> +/* RESET3 */
> +#define RESET_ISP_NIC_GPV 96
> +#define RESET_ISP_NIC_MAIN 97
> +#define RESET_ISP_NIC_VCLK 98
> +#define RESET_ISP_NIC_VOUT 99
> +#define RESET_ISP_NIC_ALL 100
> +#define RESET_VOUT 101
> +#define RESET_VOUT_VENC 102
> +/* 103 */
> +#define RESET_CVE_NIC_GPV 104
> +#define RESET_CVE_NIC_MAIN 105
> +#define RESET_CVE_NIC_GE2D 106
> +#define RESET_CVE_NIC_DW 106
> +#define RESET_CVE_NIC_CVE 108
> +#define RESET_CVE_NIC_ALL 109
> +#define RESET_CVE 110
> +/* 112-127 */
> +
> +/* RESET4 */
> +#define RESET_RTC 128
> +#define RESET_PWM_AB 129
> +#define RESET_PWM_CD 130
> +#define RESET_PWM_EF 131
> +#define RESET_PWM_GH 132
> +#define RESET_PWM_IJ 133
> +#define RESET_PWM_KL 134
> +#define RESET_PWM_MN 135
> +/* 136-137 */
> +#define RESET_UART_A 138
> +#define RESET_UART_B 139
> +#define RESET_UART_C 140
> +#define RESET_UART_D 141
> +#define RESET_UART_E 142
> +#define RESET_UART_F 143
> +#define RESET_I2C_S_A 144
> +#define RESET_I2C_M_A 145
> +#define RESET_I2C_M_B 146
> +#define RESET_I2C_M_C 147
> +#define RESET_I2C_M_D 148
> +/* 149-151 */
> +#define RESET_SD_EMMC_A 152
> +#define RESET_SD_EMMC_B 153
> +#define RESET_SD_EMMC_C 154
> +
> +/* RESET5 */
> +/* 160-172 */
> +#define RESET_BRG_NIC_NNA 173
> +#define RESET_BRG_MUX_NIC_MAIN 174
> +#define RESET_BRG_AO_NIC_ALL 175
> +/* 176-183 */
> +#define RESET_BRG_NIC_VAPB 184
> +#define RESET_BRG_NIC_SDIO_B 185
> +#define RESET_BRG_NIC_SDIO_A 186
> +#define RESET_BRG_NIC_EMMC 187
> +#define RESET_BRG_NIC_DSU 188
> +#define RESET_BRG_NIC_SYSCLK 189
> +#define RESET_BRG_NIC_MAIN 190
> +#define RESET_BRG_NIC_ALL 191
> +
> +#endif
Reviewed-by: Neil Armstrong <[email protected]>
On Thu, 14 Sep 2023 14:40:15 +0800, zelong dong wrote:
> From: Zelong Dong <[email protected]>
>
> This patchset adds Reset controller driver support for Amlogic C3 SoC.
> The RESET registers count and offset for C3 Soc are same as S4 Soc.
>
> Changes since v1:
> - remove Change-ID
> - run scripts/checkpatch.pl and fix reported warnings
> - sort dts node by base reg offset
>
> [...]
Applied patches 1 and 2 to reset/next, thanks!
[1/3] dt-bindings: reset: Add compatible and DT bindings for Amlogic C3 Reset Controller
https://git.pengutronix.de/cgit/pza/linux/commit/?id=0c0ea61c9b3a
[2/3] reset: reset-meson: add support for Amlogic C3 SoC Reset Controller
https://git.pengutronix.de/cgit/pza/linux/commit/?id=41df5d7d5e99
regards
Philipp
Hi,
On Thu, 14 Sep 2023 14:40:15 +0800, zelong dong wrote:
> From: Zelong Dong <[email protected]>
>
> This patchset adds Reset controller driver support for Amlogic C3 SoC.
> The RESET registers count and offset for C3 Soc are same as S4 Soc.
>
> Changes since v1:
> - remove Change-ID
> - run scripts/checkpatch.pl and fix reported warnings
> - sort dts node by base reg offset
>
> [...]
Thanks, Applied to https://git.kernel.org/pub/scm/linux/kernel/git/amlogic/linux.git (v6.8/arm64-dt)
[3/3] arm64: dts: amlogic: add reset controller for Amlogic C3 SoC
https://git.kernel.org/amlogic/c/a5468f5ea9a01acf29d02745abae7b82482989d4
These changes has been applied on the intermediate git tree [1].
The v6.8/arm64-dt branch will then be sent via a formal Pull Request to the Linux SoC maintainers
for inclusion in their intermediate git branches in order to be sent to Linus during
the next merge window, or sooner if it's a set of fixes.
In the cases of fixes, those will be merged in the current release candidate
kernel and as soon they appear on the Linux master branch they will be
backported to the previous Stable and Long-Stable kernels [2].
The intermediate git branches are merged daily in the linux-next tree [3],
people are encouraged testing these pre-release kernels and report issues on the
relevant mailing-lists.
If problems are discovered on those changes, please submit a signed-off-by revert
patch followed by a corrective changeset.
[1] https://git.kernel.org/pub/scm/linux/kernel/git/amlogic/linux.git
[2] https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
[3] https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git
--
Neil
Hi,
On 29/11/2023 13:26, Neil Armstrong wrote:
> Hi,
>
> On Thu, 14 Sep 2023 14:40:15 +0800, zelong dong wrote:
>> From: Zelong Dong <[email protected]>
>>
>> This patchset adds Reset controller driver support for Amlogic C3 SoC.
>> The RESET registers count and offset for C3 Soc are same as S4 Soc.
>>
>> Changes since v1:
>> - remove Change-ID
>> - run scripts/checkpatch.pl and fix reported warnings
>> - sort dts node by base reg offset
>>
>> [...]
>
> Thanks, Applied to https://git.kernel.org/pub/scm/linux/kernel/git/amlogic/linux.git (v6.8/arm64-dt)
>
> [3/3] arm64: dts: amlogic: add reset controller for Amlogic C3 SoC
> https://git.kernel.org/amlogic/c/a5468f5ea9a01acf29d02745abae7b82482989d4
I'll need to drop this patch from v6.8/arm64-dt since the amlogic,c3-reset.h is missing from
my tree, I'll postpone it to v6.9.
Thanks,
Neil
>
> These changes has been applied on the intermediate git tree [1].
>
> The v6.8/arm64-dt branch will then be sent via a formal Pull Request to the Linux SoC maintainers
> for inclusion in their intermediate git branches in order to be sent to Linus during
> the next merge window, or sooner if it's a set of fixes.
>
> In the cases of fixes, those will be merged in the current release candidate
> kernel and as soon they appear on the Linux master branch they will be
> backported to the previous Stable and Long-Stable kernels [2].
>
> The intermediate git branches are merged daily in the linux-next tree [3],
> people are encouraged testing these pre-release kernels and report issues on the
> relevant mailing-lists.
>
> If problems are discovered on those changes, please submit a signed-off-by revert
> patch followed by a corrective changeset.
>
> [1] https://git.kernel.org/pub/scm/linux/kernel/git/amlogic/linux.git
> [2] https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
> [3] https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git
>