From: "xiaoguang.xing" <[email protected]>
The first SoC in the SOPHGO series is SG2042, which contains 64 RISC-V
cores.
Signed-off-by: xiaoguang.xing <[email protected]>
Signed-off-by: Wang Chen <[email protected]>
---
arch/riscv/Kconfig.socs | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs
index 6833d01e2e70..fc7b5e6c7def 100644
--- a/arch/riscv/Kconfig.socs
+++ b/arch/riscv/Kconfig.socs
@@ -110,4 +110,14 @@ config SOC_CANAAN_K210_DTB_SOURCE
endif # ARCH_CANAAN
+config ARCH_SOPHGO
+ bool "Sophgo SoCs"
+ select SIFIVE_PLIC
+ help
+ This enables support for Sophgo SoC platform hardware.
+ SOPHGO is committed to become a provider of universal
+ computing power, focusing on the development and
+ promotion of computing power products such as AI and
+ RISC-V CPU.
+
endmenu # "SoC selection"
--
2.25.1
On 15/09/2023 09:10, Wang Chen wrote:
> From: "xiaoguang.xing" <[email protected]>
>
> The first SoC in the SOPHGO series is SG2042, which contains 64 RISC-V
> cores.
>
> Signed-off-by: xiaoguang.xing <[email protected]>
> Signed-off-by: Wang Chen <[email protected]>
Your patch threading is completely broken/missing, so this makes review
unnecessary difficult. Fix your process (e.g. use b4).
Best regards,
Krzysztof