From: Alvin Šipraga <[email protected]>
This series intends to address a problem I had when using the Si5351A as
a runtime adjustable audio bit clock. The basic issue is that the driver
in its current form unconditionally resets the PLL whenever adjusting
its rate. But this reset causes an unwanted ~1.4 ms LOW signal glitch in
the clock output.
As a remedy, a new property is added to control the reset behaviour of
the PLLs more precisely. In the process I also converted the bindings to
YAML.
Alvin Šipraga (3):
dt-bindings: clock: si5351: convert to yaml
dt-bindings: clock: si5351: add PLL reset mode property
clk: si5351: allow PLLs to be adjusted without reset
.../bindings/clock/silabs,si5351.txt | 126 --------
.../bindings/clock/silabs,si5351.yaml | 270 ++++++++++++++++++
drivers/clk/clk-si5351.c | 47 ++-
include/linux/platform_data/si5351.h | 2 +
4 files changed, 316 insertions(+), 129 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/clock/silabs,si5351.txt
create mode 100644 Documentation/devicetree/bindings/clock/silabs,si5351.yaml
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2.41.0