2023-09-22 01:06:02

by Anshuman Khandual

Subject: [PATCH V7 0/3] coresight: etm: Make cycle count threshold user configurable

This series makes ETM TRCCCCTRL based 'cc_threshold' user configurable via
the perf event attribute. But first, this implements an errata work around
affecting ETM TRCIDR3.CCITMIN value on certain cpus, overriding the field.

This series applies on coresight/for-next/queue.

Cc: Catalin Marinas <[email protected]>
Cc: Will Deacon <[email protected]>
Cc: Suzuki K Poulose <[email protected]>
Cc: Mike Leach <[email protected]>
Cc: James Clark <[email protected]>
Cc: Leo Yan <[email protected]>
Cc: Jonathan Corbet <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]

Changes in V7:

- Changed commit message for the second patch adding cc_threshold

Changes in V6:

https://lore.kernel.org/all/[email protected]/

- Renamed etm4_core_reads_wrong_ccitmin() as etm4_fixup_wrong_ccitmin()
- Moved drvdata->ccitmin fixup inside etm4_fixup_wrong_ccitmin()

Changes in V5:

https://lore.kernel.org/all/[email protected]/
https://lore.kernel.org/all/[email protected]/

- Replaced 'where as' with single word 'whereas'
- Reworked 'cc_threshold' fallback to ETM_CYC_THRESHOLD_DEFAULT

Changes in V4:

https://lore.kernel.org/all/[email protected]/

- Fixed a typo s/rangess/ranges,
- Renamed etm4_work_around_wrong_ccitmin() as etm4_core_reads_wrong_ccitmin()
- Moved drvdata->ccitmin value check for 256 inside etm4_core_reads_wrong_ccitmin()
- Moved the comment inside etm4_core_reads_wrong_ccitmin()

Changes in V3:

https://lore.kernel.org/all/[email protected]/

- Added errata work around affecting TRCIDR3.CCITMIN
- Split the document update into a separate patch

Changes in V2:

https://lore.kernel.org/all/[email protected]/

- s/treshhold/threshold

Changes in V1:

https://lore.kernel.org/all/[email protected]/

Anshuman Khandual (3):
coresight: etm: Override TRCIDR3.CCITMIN on errata affected cpus
coresight: etm: Make cycle count threshold user configurable
Documentation: coresight: Add cc_threshold tunable

Documentation/arch/arm64/silicon-errata.rst | 10 ++++
Documentation/trace/coresight/coresight.rst | 4 ++
.../hwtracing/coresight/coresight-etm-perf.c | 2 +
.../coresight/coresight-etm4x-core.c | 46 ++++++++++++++++++-
4 files changed, 60 insertions(+), 2 deletions(-)

--
2.25.1

2023-10-16 23:04:14

by Suzuki K Poulose

Subject: Re: [PATCH V7 0/3] coresight: etm: Make cycle count threshold user configurable

On Thu, 21 Sep 2023 09:06:28 +0530, Anshuman Khandual wrote:
> This series makes ETM TRCCCCTRL based 'cc_threshold' user configurable via
> the perf event attribute. But first, this implements an errata work around
> affecting ETM TRCIDR3.CCITMIN value on certain cpus, overriding the field.
>
> This series applies on coresight/for-next/queue.
>
> Cc: Catalin Marinas <[email protected]>
> Cc: Will Deacon <[email protected]>
> Cc: Suzuki K Poulose <[email protected]>
> Cc: Mike Leach <[email protected]>
> Cc: James Clark <[email protected]>
> Cc: Leo Yan <[email protected]>
> Cc: Jonathan Corbet <[email protected]>
> Cc: [email protected]
> Cc: [email protected]
> Cc: [email protected]
> Cc: [email protected]
>
> [...]

Applied, thanks!

[1/3] coresight: etm: Override TRCIDR3.CCITMIN on errata affected cpus
https://git.kernel.org/coresight/c/0f55b43dedcd
[2/3] coresight: etm: Make cycle count threshold user configurable
https://git.kernel.org/coresight/c/0cf805fec179
[3/3] Documentation: coresight: Add cc_threshold tunable
https://git.kernel.org/coresight/c/2b690bebb569

Best regards,
--
Suzuki K Poulose <[email protected]>