2023-09-23 01:18:28

by Luca Weiss

Subject: [PATCH v2 0/3] Add blsp1_i2c6 and blsp1_uart2 to MSM8226 SoC

Add the I2C bus and UART interface found on the MSM8226. For the I2C bus
we also first need to add the pinctrl function in the driver.

Signed-off-by: Luca Weiss <[email protected]>
---
Changes in v2:
- Add binding change patch
- Adjust property order in dtsi
- Link to v1: https://lore.kernel.org/r/[email protected]

---
Luca Weiss (3):
dt-bindings: pinctrl: qcom,msm8226: Add blsp_i2c6 function
pinctrl: qcom: msm8226: Add blsp_i2c6 function
ARM: dts: qcom: msm8226: Add blsp1_i2c6 and blsp1_uart2

.../bindings/pinctrl/qcom,msm8226-pinctrl.yaml | 4 +--
arch/arm/boot/dts/qcom/qcom-msm8226.dtsi | 33 ++++++++++++++++++++++
drivers/pinctrl/qcom/pinctrl-msm8226.c | 8 ++++--
3 files changed, 41 insertions(+), 4 deletions(-)
---
base-commit: 940fcc189c51032dd0282cbee4497542c982ac59
change-id: 20230902-msm8226-i2c6-0f7d74dafa8b

Best regards,
--
Luca Weiss <[email protected]>

2023-09-23 03:10:45

by Luca Weiss

Subject: [PATCH v2 3/3] ARM: dts: qcom: msm8226: Add blsp1_i2c6 and blsp1_uart2

Add more busses found on msm8226 SoC.

Signed-off-by: Luca Weiss <[email protected]>
---
arch/arm/boot/dts/qcom/qcom-msm8226.dtsi | 33 ++++++++++++++++++++++++++++++++
1 file changed, 33 insertions(+)

diff --git a/arch/arm/boot/dts/qcom/qcom-msm8226.dtsi b/arch/arm/boot/dts/qcom/qcom-msm8226.dtsi
index 44f3f0127fd7..82e830e9d254 100644
--- a/arch/arm/boot/dts/qcom/qcom-msm8226.dtsi
+++ b/arch/arm/boot/dts/qcom/qcom-msm8226.dtsi
@@ -230,6 +230,17 @@ blsp1_uart1: serial@f991d000 {
status = "disabled";
};

+ blsp1_uart2: serial@f991e000 {
+ compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
+ reg = <0xf991e000 0x1000>;
+ interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
+ <&gcc GCC_BLSP1_AHB_CLK>;
+ clock-names = "core",
+ "iface";
+ status = "disabled";
+ };
+
blsp1_uart3: serial@f991f000 {
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
reg = <0xf991f000 0x1000>;
@@ -313,6 +324,21 @@ blsp1_i2c5: i2c@f9927000 {
#size-cells = <0>;
};

+ blsp1_i2c6: i2c@f9928000 {
+ compatible = "qcom,i2c-qup-v2.1.1";
+ reg = <0xf9928000 0x1000>;
+ interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>,
+ <&gcc GCC_BLSP1_AHB_CLK>;
+ clock-names = "core",
+ "iface";
+ pinctrl-0 = <&blsp1_i2c6_pins>;
+ pinctrl-names = "default";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
cci: cci@fda0c000 {
compatible = "qcom,msm8226-cci";
#address-cells = <1>;
@@ -460,6 +486,13 @@ blsp1_i2c5_pins: blsp1-i2c5-state {
bias-disable;
};

+ blsp1_i2c6_pins: blsp1-i2c6-state {
+ pins = "gpio22", "gpio23";
+ function = "blsp_i2c6";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
cci_default: cci-default-state {
pins = "gpio29", "gpio30";
function = "cci_i2c0";

--
2.42.0

2023-09-23 23:35:48

by Dmitry Baryshkov

Subject: Re: [PATCH v2 3/3] ARM: dts: qcom: msm8226: Add blsp1_i2c6 and blsp1_uart2

On Fri, 22 Sept 2023 at 19:56, Luca Weiss <[email protected]> wrote:
>
> Add more busses found on msm8226 SoC.
>
> Signed-off-by: Luca Weiss <[email protected]>
> ---
> arch/arm/boot/dts/qcom/qcom-msm8226.dtsi | 33 ++++++++++++++++++++++++++++++++
> 1 file changed, 33 insertions(+)
>

Reviewed-by: Dmitry Baryshkov <[email protected]>

--
With best wishes
Dmitry

2023-09-27 09:57:38

by Linus Walleij

Subject: Re: [PATCH v2 0/3] Add blsp1_i2c6 and blsp1_uart2 to MSM8226 SoC

On Fri, Sep 22, 2023 at 6:56 PM Luca Weiss <[email protected]> wrote:

> Add the I2C bus and UART interface found on the MSM8226. For the I2C bus
> we also first need to add the pinctrl function in the driver.
>
> Signed-off-by: Luca Weiss <[email protected]>

v2 looks fine and ACKs in place, so patches applied!

Yours,
Linus Walleij