On Sat, Aug 19, 2023 at 05:50:01AM -0500, Adam Ford wrote:
> Commit 16c984524862 ("arm64: dts: imx8mp: don't initialize audio clocks
> from CCM node") removed the Audio clocks from the main clock node, because
> the intent is to force people to setup the audio PLL clocks per board
> instead of having a common set of rates, since not all boards may use
> the various audio PLL clocks in the same way.
>
> Unfortunately, with this parenting removed, the SDMA2 and SDMA3
> clocks were slowed to 24MHz because the SDMA2/3 clocks are controlled
> via the audio_blk_ctrl which is clocked from IMX8MP_CLK_AUDIO_ROOT,
> and that clock is enabled by pgc_audio.
>
> Per the TRM, "The SDMA2/3 target frequency is 400MHz IPG and 400MHz
> AHB, always 1:1 mode, to make sure there is enough throughput for all
> the audio use cases."
>
> Instead of cluttering the clock node, place the clock rate and parent
> information into the pgc_audio node.
>
> With the parenting and clock rates restored for IMX8MP_CLK_AUDIO_AHB,
> and IMX8MP_CLK_AUDIO_AXI_SRC, it appears the SDMA2 and SDMA3 run at
> 400MHz again.
>
> Fixes: 16c984524862 ("arm64: dts: imx8mp: don't initialize audio clocks from CCM node")
> Signed-off-by: Adam Ford <[email protected]>
> Reviewed-by: Lucas Stach <[email protected]>
> Reviewed-by: Fabio Estevam <[email protected]>
Applied both, thanks!