This series adds support for:
- DisplayPort for J784S4-EVM
- Displayport and HDMI for AM69-SK platform
NOTE: Patch 4/5 introduces the following dtc warning which can be ignored
since its behind W=1 check:
Warning (graph_child_address): /bus@100000/dss@4a00000/ports: graph node
has single child node 'port@0', #address-cells/#size-cells are not
necessary
(This is more accurate description for port and the dtc check should not
differentiate between port@0 and port@1.[3])
Changelog v9->v10:
- Remove duplicate properties from dp0_ports node in main file.
- Add reg for the port even though there is only single port in dss_port
since its more accurate description for the port.
- Carry the R-by tags from v9.
Changelog v8->v9:
- Fix compatible of serdes_ln_ctrl node
- Fix extra new lines across nodes
- Fix node-names to keep them generic
Changelog v7->v8:
- rebase on tag next-20230731
- add AM69 display support
- fix commit heading for patch [2/5]
Changelog v6->v7:
- change compatible for scm_conf to 'simple-bus'
- drop main_cpsw node due to driver dependency on [2]
Changelog v5->v6:
- Change header file according to [1].
- Add idle-state property in serdes_ln_ctrl node.
- Fix dtbs_check warning due to clock-frequency property in serdes_refclk
node by disabling the node in main.dtsi and enabling it in board file
when the clock-frequency node is actually added.
Changelog v4->v5:
- rebased the patches on linux-next tip.
Changelog v3->v4:
- add reg property to serdes_ln_ctrl and fix the node name again to
get rid of dtbs_check error.
- reorder reg, reg-names and ranges property for main_cpsw1.
- correct the order for clocks in serdes_wiz nodes to fix dtbs_check
warnings.
- fix indentation in reg, reg-names and clock property for dss node.
- add comments for the reg type in dss registers.
Changelog v3->v2:
- fix dtc warnings for 'scm_conf' and 'serdes_ln_ctrl' nodes
(Checked all the changes of the series with W=12 option during build)
- added clock-frequency for serdes_refclk along with other EVM changes
This refclk is being used by all the instances of serdes_wiz which
are disabled by default. So configuring refclk when the serdes nodes
are used for the first time is okay.
Changelog v1->v2:
- Moved J784S4 EVM changes together to the last patch
(Suggested by Andrew)
v9 patch link:
<https://lore.kernel.org/all/[email protected]/>
[1]: <https://lore.kernel.org/all/[email protected]/>
[2]: <https://lore.kernel.org/all/[email protected]/>
[3]: <https://lore.kernel.org/all/[email protected]/>
Dasnavis Sabiya (1):
arm64: dts: ti: k3-am69-sk: Add DP and HDMI support
Rahul T R (2):
arm64: dts: ti: k3-j784s4-main: Add DSS and DP-bridge node
arm64: dts: ti: k3-j784s4-evm: Enable DisplayPort-0
Siddharth Vadapalli (2):
arm64: dts: ti: k3-j784s4-main: Add system controller and SERDES lane
mux
arm64: dts: ti: k3-j784s4-main: Add WIZ and SERDES PHY nodes
arch/arm64/boot/dts/ti/k3-am69-sk.dts | 234 ++++++++++++++++++
arch/arm64/boot/dts/ti/k3-j784s4-evm.dts | 124 ++++++++++
arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 265 +++++++++++++++++++++
3 files changed, 623 insertions(+)
--
2.25.1
From: Siddharth Vadapalli <[email protected]>
The system controller node manages the CTRL_MMR0 region.
Add serdes_ln_ctrl node which is used for controlling the SERDES lane mux.
Signed-off-by: Siddharth Vadapalli <[email protected]>
[[email protected]: Fix serdes_ln_ctrl node]
Signed-off-by: Jayesh Choudhary <[email protected]>
---
arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 40 ++++++++++++++++++++++
1 file changed, 40 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
index efed2d683f63..6d9a5a91fa75 100644
--- a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
@@ -5,6 +5,10 @@
* Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
*/
+#include <dt-bindings/mux/mux.h>
+
+#include "k3-serdes.h"
+
&cbass_main {
msmc_ram: sram@70000000 {
compatible = "mmio-sram";
@@ -26,6 +30,42 @@ l3cache-sram@200000 {
};
};
+ scm_conf: bus@100000 {
+ compatible = "simple-bus";
+ reg = <0x00 0x00100000 0x00 0x1c000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x00 0x00 0x00100000 0x1c000>;
+
+ serdes_ln_ctrl: mux-controller@4080 {
+ compatible = "reg-mux";
+ reg = <0x00004080 0x30>;
+ #mux-control-cells = <1>;
+ mux-reg-masks = <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */
+ <0x4088 0x3>, <0x408c 0x3>, /* SERDES0 lane2/3 select */
+ <0x4090 0x3>, <0x4094 0x3>, /* SERDES1 lane0/1 select */
+ <0x4098 0x3>, <0x409c 0x3>, /* SERDES1 lane2/3 select */
+ <0x40a0 0x3>, <0x40a4 0x3>, /* SERDES2 lane0/1 select */
+ <0x40a8 0x3>, <0x40ac 0x3>; /* SERDES2 lane2/3 select */
+ idle-states = <J784S4_SERDES0_LANE0_PCIE1_LANE0>,
+ <J784S4_SERDES0_LANE1_PCIE1_LANE1>,
+ <J784S4_SERDES0_LANE2_IP3_UNUSED>,
+ <J784S4_SERDES0_LANE3_USB>,
+ <J784S4_SERDES1_LANE0_PCIE0_LANE0>,
+ <J784S4_SERDES1_LANE1_PCIE0_LANE1>,
+ <J784S4_SERDES1_LANE2_PCIE0_LANE2>,
+ <J784S4_SERDES1_LANE3_PCIE0_LANE3>,
+ <J784S4_SERDES2_LANE0_IP2_UNUSED>,
+ <J784S4_SERDES2_LANE1_IP2_UNUSED>,
+ <J784S4_SERDES2_LANE2_QSGMII_LANE1>,
+ <J784S4_SERDES2_LANE3_QSGMII_LANE2>,
+ <J784S4_SERDES4_LANE0_EDP_LANE0>,
+ <J784S4_SERDES4_LANE1_EDP_LANE1>,
+ <J784S4_SERDES4_LANE2_EDP_LANE2>,
+ <J784S4_SERDES4_LANE3_EDP_LANE3>;
+ };
+ };
+
gic500: interrupt-controller@1800000 {
compatible = "arm,gic-v3";
#address-cells = <2>;
--
2.25.1