2023-09-27 15:12:43

by Jayesh Choudhary

Subject: [PATCH v10 3/5] arm64: dts: ti: k3-j784s4-main: Add DSS and DP-bridge node

From: Rahul T R <[email protected]>

Add DSS and DP-bridge node for J784S4 SoC. DSS IP in J784S4 is
same as DSS IP in J721E, so same compatible is being used.
The DP is Cadence MHDP8546.

Signed-off-by: Rahul T R <[email protected]>
[[email protected]: move dss & mhdp node together in main, fix dss node]
Signed-off-by: Jayesh Choudhary <[email protected]>
Reviewed-by: Aradhya Bhatia <[email protected]>
---
arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 61 ++++++++++++++++++++++
1 file changed, 61 insertions(+)

diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
index a0e4d8808693..5ae11b0d5d0a 100644
--- a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
@@ -1772,4 +1772,65 @@ c71_3: dsp@67800000 {
firmware-name = "j784s4-c71_3-fw";
status = "disabled";
};
+
+ mhdp: bridge@a000000 {
+ compatible = "ti,j721e-mhdp8546";
+ reg = <0x0 0xa000000 0x0 0x30a00>,
+ <0x0 0x4f40000 0x0 0x20>;
+ reg-names = "mhdptx", "j721e-intg";
+ clocks = <&k3_clks 217 11>;
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 614 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&k3_pds 217 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
+
+ dp0_ports: ports {
+ };
+ };
+
+ dss: dss@4a00000 {
+ compatible = "ti,j721e-dss";
+ reg = <0x00 0x04a00000 0x00 0x10000>, /* common_m */
+ <0x00 0x04a10000 0x00 0x10000>, /* common_s0*/
+ <0x00 0x04b00000 0x00 0x10000>, /* common_s1*/
+ <0x00 0x04b10000 0x00 0x10000>, /* common_s2*/
+ <0x00 0x04a20000 0x00 0x10000>, /* vidl1 */
+ <0x00 0x04a30000 0x00 0x10000>, /* vidl2 */
+ <0x00 0x04a50000 0x00 0x10000>, /* vid1 */
+ <0x00 0x04a60000 0x00 0x10000>, /* vid2 */
+ <0x00 0x04a70000 0x00 0x10000>, /* ovr1 */
+ <0x00 0x04a90000 0x00 0x10000>, /* ovr2 */
+ <0x00 0x04ab0000 0x00 0x10000>, /* ovr3 */
+ <0x00 0x04ad0000 0x00 0x10000>, /* ovr4 */
+ <0x00 0x04a80000 0x00 0x10000>, /* vp1 */
+ <0x00 0x04aa0000 0x00 0x10000>, /* vp1 */
+ <0x00 0x04ac0000 0x00 0x10000>, /* vp1 */
+ <0x00 0x04ae0000 0x00 0x10000>, /* vp4 */
+ <0x00 0x04af0000 0x00 0x10000>; /* wb */
+ reg-names = "common_m", "common_s0",
+ "common_s1", "common_s2",
+ "vidl1", "vidl2","vid1","vid2",
+ "ovr1", "ovr2", "ovr3", "ovr4",
+ "vp1", "vp2", "vp3", "vp4",
+ "wb";
+ clocks = <&k3_clks 218 0>,
+ <&k3_clks 218 2>,
+ <&k3_clks 218 5>,
+ <&k3_clks 218 14>,
+ <&k3_clks 218 18>;
+ clock-names = "fck", "vp1", "vp2", "vp3", "vp4";
+ power-domains = <&k3_pds 218 TI_SCI_PD_EXCLUSIVE>;
+ interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "common_m",
+ "common_s0",
+ "common_s1",
+ "common_s2";
+ status = "disabled";
+
+ dss_ports: ports {
+ };
+ };
};
--
2.25.1

2023-09-27 21:14:11

by Nishanth Menon

Subject: Re: [PATCH v10 3/5] arm64: dts: ti: k3-j784s4-main: Add DSS and DP-bridge node

On 17:41-20230927, Jayesh Choudhary wrote:
> From: Rahul T R <[email protected]>
>
> Add DSS and DP-bridge node for J784S4 SoC. DSS IP in J784S4 is
> same as DSS IP in J721E, so same compatible is being used.
> The DP is Cadence MHDP8546.
>
> Signed-off-by: Rahul T R <[email protected]>
> [[email protected]: move dss & mhdp node together in main, fix dss node]
> Signed-off-by: Jayesh Choudhary <[email protected]>
> Reviewed-by: Aradhya Bhatia <[email protected]>
> ---
> arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 61 ++++++++++++++++++++++
> 1 file changed, 61 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
> index a0e4d8808693..5ae11b0d5d0a 100644
> --- a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
> @@ -1772,4 +1772,65 @@ c71_3: dsp@67800000 {
> firmware-name = "j784s4-c71_3-fw";
> status = "disabled";
> };
> +
> + mhdp: bridge@a000000 {
> + compatible = "ti,j721e-mhdp8546";
> + reg = <0x0 0xa000000 0x0 0x30a00>,
> + <0x0 0x4f40000 0x0 0x20>;
> + reg-names = "mhdptx", "j721e-intg";
> + clocks = <&k3_clks 217 11>;
> + interrupt-parent = <&gic500>;
> + interrupts = <GIC_SPI 614 IRQ_TYPE_LEVEL_HIGH>;
> + power-domains = <&k3_pds 217 TI_SCI_PD_EXCLUSIVE>;
> + status = "disabled";

Document why disabled.

> +
> + dp0_ports: ports {
> + };

Document why empty node

> + };
> +
> + dss: dss@4a00000 {
> + compatible = "ti,j721e-dss";
> + reg = <0x00 0x04a00000 0x00 0x10000>, /* common_m */
> + <0x00 0x04a10000 0x00 0x10000>, /* common_s0*/
> + <0x00 0x04b00000 0x00 0x10000>, /* common_s1*/
> + <0x00 0x04b10000 0x00 0x10000>, /* common_s2*/
> + <0x00 0x04a20000 0x00 0x10000>, /* vidl1 */
> + <0x00 0x04a30000 0x00 0x10000>, /* vidl2 */
> + <0x00 0x04a50000 0x00 0x10000>, /* vid1 */
> + <0x00 0x04a60000 0x00 0x10000>, /* vid2 */
> + <0x00 0x04a70000 0x00 0x10000>, /* ovr1 */
> + <0x00 0x04a90000 0x00 0x10000>, /* ovr2 */
> + <0x00 0x04ab0000 0x00 0x10000>, /* ovr3 */
> + <0x00 0x04ad0000 0x00 0x10000>, /* ovr4 */
> + <0x00 0x04a80000 0x00 0x10000>, /* vp1 */
> + <0x00 0x04aa0000 0x00 0x10000>, /* vp1 */
> + <0x00 0x04ac0000 0x00 0x10000>, /* vp1 */
> + <0x00 0x04ae0000 0x00 0x10000>, /* vp4 */
> + <0x00 0x04af0000 0x00 0x10000>; /* wb */
> + reg-names = "common_m", "common_s0",
> + "common_s1", "common_s2",
> + "vidl1", "vidl2","vid1","vid2",
> + "ovr1", "ovr2", "ovr3", "ovr4",
> + "vp1", "vp2", "vp3", "vp4",
> + "wb";
> + clocks = <&k3_clks 218 0>,
> + <&k3_clks 218 2>,
> + <&k3_clks 218 5>,
> + <&k3_clks 218 14>,
> + <&k3_clks 218 18>;
> + clock-names = "fck", "vp1", "vp2", "vp3", "vp4";
> + power-domains = <&k3_pds 218 TI_SCI_PD_EXCLUSIVE>;
> + interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "common_m",
> + "common_s0",
> + "common_s1",
> + "common_s2";
> + status = "disabled";

Same

> +
> + dss_ports: ports {

Same

> + };
> + };
> };
> --
> 2.25.1
>

--
Regards,
Nishanth Menon
Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3 1A34 DDB5 849D 1736 249D

2023-10-04 11:14:20

by Jayesh Choudhary

Subject: Re: [PATCH v10 3/5] arm64: dts: ti: k3-j784s4-main: Add DSS and DP-bridge node

On 27/09/23 17:54, Nishanth Menon wrote:
> On 17:41-20230927, Jayesh Choudhary wrote:
>> From: Rahul T R <[email protected]>
>>
>> Add DSS and DP-bridge node for J784S4 SoC. DSS IP in J784S4 is
>> same as DSS IP in J721E, so same compatible is being used.
>> The DP is Cadence MHDP8546.
>>
>> Signed-off-by: Rahul T R <[email protected]>
>> [[email protected]: move dss & mhdp node together in main, fix dss node]
>> Signed-off-by: Jayesh Choudhary <[email protected]>
>> Reviewed-by: Aradhya Bhatia <[email protected]>
>> ---
>> arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 61 ++++++++++++++++++++++
>> 1 file changed, 61 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
>> index a0e4d8808693..5ae11b0d5d0a 100644
>> --- a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
>> +++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
>> @@ -1772,4 +1772,65 @@ c71_3: dsp@67800000 {
>> firmware-name = "j784s4-c71_3-fw";
>> status = "disabled";
>> };
>> +
>> + mhdp: bridge@a000000 {
>> + compatible = "ti,j721e-mhdp8546";
>> + reg = <0x0 0xa000000 0x0 0x30a00>,
>> + <0x0 0x4f40000 0x0 0x20>;
>> + reg-names = "mhdptx", "j721e-intg";
>> + clocks = <&k3_clks 217 11>;
>> + interrupt-parent = <&gic500>;
>> + interrupts = <GIC_SPI 614 IRQ_TYPE_LEVEL_HIGH>;
>> + power-domains = <&k3_pds 217 TI_SCI_PD_EXCLUSIVE>;
>> + status = "disabled";
>
> Document why disabled.

Okay.

>
>> +
>> + dp0_ports: ports {
>> + };
>
> Document why empty node

I will mention that the remote-endpoint are on the board so all the
properties are defined there together. So keeping it empty here.

Other way could be to add #address-cells and #size-cell here with port
child-node. And its remote end point added in the board file. But node
would still be incomplete here.

Warm Regards,
-Jayesh

>
>> + };
>> +
>> + dss: dss@4a00000 {
>> + compatible = "ti,j721e-dss";
>> + reg = <0x00 0x04a00000 0x00 0x10000>, /* common_m */
>> + <0x00 0x04a10000 0x00 0x10000>, /* common_s0*/
>> + <0x00 0x04b00000 0x00 0x10000>, /* common_s1*/
>> + <0x00 0x04b10000 0x00 0x10000>, /* common_s2*/
>> + <0x00 0x04a20000 0x00 0x10000>, /* vidl1 */
>> + <0x00 0x04a30000 0x00 0x10000>, /* vidl2 */
>> + <0x00 0x04a50000 0x00 0x10000>, /* vid1 */
>> + <0x00 0x04a60000 0x00 0x10000>, /* vid2 */
>> + <0x00 0x04a70000 0x00 0x10000>, /* ovr1 */
>> + <0x00 0x04a90000 0x00 0x10000>, /* ovr2 */
>> + <0x00 0x04ab0000 0x00 0x10000>, /* ovr3 */
>> + <0x00 0x04ad0000 0x00 0x10000>, /* ovr4 */
>> + <0x00 0x04a80000 0x00 0x10000>, /* vp1 */
>> + <0x00 0x04aa0000 0x00 0x10000>, /* vp1 */
>> + <0x00 0x04ac0000 0x00 0x10000>, /* vp1 */
>> + <0x00 0x04ae0000 0x00 0x10000>, /* vp4 */
>> + <0x00 0x04af0000 0x00 0x10000>; /* wb */
>> + reg-names = "common_m", "common_s0",
>> + "common_s1", "common_s2",
>> + "vidl1", "vidl2","vid1","vid2",
>> + "ovr1", "ovr2", "ovr3", "ovr4",
>> + "vp1", "vp2", "vp3", "vp4",
>> + "wb";
>> + clocks = <&k3_clks 218 0>,
>> + <&k3_clks 218 2>,
>> + <&k3_clks 218 5>,
>> + <&k3_clks 218 14>,
>> + <&k3_clks 218 18>;
>> + clock-names = "fck", "vp1", "vp2", "vp3", "vp4";
>> + power-domains = <&k3_pds 218 TI_SCI_PD_EXCLUSIVE>;
>> + interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
>> + interrupt-names = "common_m",
>> + "common_s0",
>> + "common_s1",
>> + "common_s2";
>> + status = "disabled";
>
> Same
>
>> +
>> + dss_ports: ports {
>
> Same
>
>> + };
>> + };
>> };
>> --
>> 2.25.1
>>
>