2023-09-28 22:17:26

by Christophe Roullier

Subject: [PATCH v2 00/12] Series to deliver Ethernets for STM32MP13

STM32MP13 is STM32 SOC with 2 GMACs instances
This board have 2 RMII phy:
-Ethernet1: RMII with crystal
-Ethernet2: RMII without crystal
Rework dwmac glue to simplify management for next stm32

-V2: Update from remark of Andrew Lunn (split commit into a number of smaller patches)
Update from Conor Dooley (yaml documentation)

Christophe Roullier (12):
dt-bindings: net: add STM32MP13 compatible in documentation for stm32
dt-bindings: net: add new property st,ext-phyclk in documentation for
stm32
dt-bindings: net: add phy-supply property for stm32
net: ethernet: stmmac: rework glue to simplify management for next
stm32
net: ethernet: stmmac: add management of stm32mp13 for stm32
net: ethernet: stmmac: stm32: update config management for phy wo
cristal
net: ethernet: stm32: clean the way to manage wol irqwake
net: ethernet: stmmac: stm32: support the phy-supply regulator binding
ARM: dts: stm32: add ethernet1 and ethernet2 support on stm32mp13
ARM: dts: stm32: add ethernet1/2 RMII pins for STM32MP13F-DK board
ARM: dts: stm32: add ethernet1 and ethernet2 for STM32MP135F-DK board
ARM: multi_v7_defconfig: Add MCP23S08 pinctrl support

.../devicetree/bindings/net/stm32-dwmac.yaml | 90 ++++++-
arch/arm/boot/dts/st/stm32mp13-pinctrl.dtsi | 71 ++++++
arch/arm/boot/dts/st/stm32mp131.dtsi | 31 +++
arch/arm/boot/dts/st/stm32mp133.dtsi | 30 +++
arch/arm/boot/dts/st/stm32mp135f-dk.dts | 48 ++++
arch/arm/configs/multi_v7_defconfig | 1 +
.../net/ethernet/stmicro/stmmac/dwmac-stm32.c | 229 +++++++++++++-----
7 files changed, 425 insertions(+), 75 deletions(-)

--
2.25.1

2023-09-29 01:04:31

by Christophe Roullier

Subject: [PATCH v2 11/12] ARM: dts: stm32: add ethernet1 and ethernet2 for STM32MP135F-DK board

Add dual Ethernet:
-Ethernet1: RMII with crystal
-Ethernet2: RMII without crystal
PHYs used are SMSC (LAN8742A)

With Ethernet1, we can performed WoL from PHY instead of GMAC point of view.
(in this case IRQ for WoL is managed as wakeup pin and configured
in OS secure).

Signed-off-by: Christophe Roullier <[email protected]>
---
arch/arm/boot/dts/st/stm32mp135f-dk.dts | 48 +++++++++++++++++++++++++
1 file changed, 48 insertions(+)

diff --git a/arch/arm/boot/dts/st/stm32mp135f-dk.dts b/arch/arm/boot/dts/st/stm32mp135f-dk.dts
index eea740d097c72..1316cc16f8dd9 100644
--- a/arch/arm/boot/dts/st/stm32mp135f-dk.dts
+++ b/arch/arm/boot/dts/st/stm32mp135f-dk.dts
@@ -19,6 +19,8 @@ / {
compatible = "st,stm32mp135f-dk", "st,stm32mp135";

aliases {
+ ethernet0 = &ethernet1;
+ ethernet1 = &ethernet2;
serial0 = &uart4;
serial1 = &usart1;
serial2 = &uart8;
@@ -93,6 +95,52 @@ channel@12 {
};
};

+&ethernet1 {
+ status = "okay";
+ pinctrl-0 = <&eth1_rmii_pins_a>;
+ pinctrl-1 = <&eth1_rmii_sleep_pins_a>;
+ pinctrl-names = "default", "sleep";
+ phy-mode = "rmii";
+ max-speed = <100>;
+ phy-handle = <&phy0_eth1>;
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "snps,dwmac-mdio";
+
+ phy0_eth1: ethernet-phy@0 {
+ compatible = "ethernet-phy-id0007.c131";
+ reset-gpios = <&mcp23017 9 GPIO_ACTIVE_LOW>;
+ reg = <0>;
+ wakeup-source;
+ };
+ };
+};
+
+&ethernet2 {
+ status = "okay";
+ pinctrl-0 = <&eth2_rmii_pins_a>;
+ pinctrl-1 = <&eth2_rmii_sleep_pins_a>;
+ pinctrl-names = "default", "sleep";
+ phy-mode = "rmii";
+ max-speed = <100>;
+ phy-handle = <&phy0_eth2>;
+ st,ext-phyclk;
+ phy-supply = <&scmi_v3v3_sw>;
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "snps,dwmac-mdio";
+ phy0_eth2: ethernet-phy@0 {
+ compatible = "ethernet-phy-id0007.c131";
+ reset-gpios = <&mcp23017 10 GPIO_ACTIVE_LOW>;
+ reg = <0>;
+ };
+ };
+};
+
&i2c1 {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&i2c1_pins_a>;
--
2.25.1