IPQ8074 comes in 2 families:
* IPQ8070A/IPQ8071A (Acorn) up to 1.4GHz
* IPQ8172/IPQ8173/IPQ8174 (Oak) up to 1.4GHz
* IPQ8072A/IPQ8074A/IPQ8076A/IPQ8078A (Hawkeye) up to 2.2GHz
So, in order to be able to share one OPP table lets add support for IPQ8074
family based of SMEM SoC ID-s as speedbin fuse is always 0 on IPQ8074.
IPQ8074 compatible is blacklisted from DT platdev as the cpufreq device
will get created by NVMEM CPUFreq driver.
Signed-off-by: Robert Marko <[email protected]>
---
Changes in v4:
* Add support for IPQ8174 (Oak) family
Changes in v3:
* Use enum for SoC versions
Changes in v2:
* Print an error if SMEM ID is not part of the IPQ8074 family
and restrict the speed to Acorn variant (1.4GHz)
---
drivers/cpufreq/cpufreq-dt-platdev.c | 1 +
drivers/cpufreq/qcom-cpufreq-nvmem.c | 48 ++++++++++++++++++++++++++++
2 files changed, 49 insertions(+)
diff --git a/drivers/cpufreq/cpufreq-dt-platdev.c b/drivers/cpufreq/cpufreq-dt-platdev.c
index 02ec58a8603b..cc3ccc1519c3 100644
--- a/drivers/cpufreq/cpufreq-dt-platdev.c
+++ b/drivers/cpufreq/cpufreq-dt-platdev.c
@@ -179,6 +179,7 @@ static const struct of_device_id blocklist[] __initconst = {
{ .compatible = "ti,am62a7", },
{ .compatible = "qcom,ipq8064", },
+ { .compatible = "qcom,ipq8074", },
{ .compatible = "qcom,apq8064", },
{ .compatible = "qcom,msm8974", },
{ .compatible = "qcom,msm8960", },
diff --git a/drivers/cpufreq/qcom-cpufreq-nvmem.c b/drivers/cpufreq/qcom-cpufreq-nvmem.c
index 84d7033e5efe..3fa12648ceb6 100644
--- a/drivers/cpufreq/qcom-cpufreq-nvmem.c
+++ b/drivers/cpufreq/qcom-cpufreq-nvmem.c
@@ -30,6 +30,11 @@
#include <dt-bindings/arm/qcom,ids.h>
+enum ipq8074_versions {
+ IPQ8074_HAWKEYE_VERSION = 0,
+ IPQ8074_ACORN_VERSION,
+};
+
struct qcom_cpufreq_drv;
struct qcom_cpufreq_match_data {
@@ -203,6 +208,44 @@ static int qcom_cpufreq_krait_name_version(struct device *cpu_dev,
return ret;
}
+static int qcom_cpufreq_ipq8074_name_version(struct device *cpu_dev,
+ struct nvmem_cell *speedbin_nvmem,
+ char **pvs_name,
+ struct qcom_cpufreq_drv *drv)
+{
+ u32 msm_id;
+ int ret;
+ *pvs_name = NULL;
+
+ ret = qcom_smem_get_soc_id(&msm_id);
+ if (ret)
+ return ret;
+
+ switch (msm_id) {
+ case QCOM_ID_IPQ8070A:
+ case QCOM_ID_IPQ8071A:
+ case QCOM_ID_IPQ8172:
+ case QCOM_ID_IPQ8173:
+ case QCOM_ID_IPQ8174:
+ drv->versions = BIT(IPQ8074_ACORN_VERSION);
+ break;
+ case QCOM_ID_IPQ8072A:
+ case QCOM_ID_IPQ8074A:
+ case QCOM_ID_IPQ8076A:
+ case QCOM_ID_IPQ8078A:
+ drv->versions = BIT(IPQ8074_HAWKEYE_VERSION);
+ break;
+ default:
+ dev_err(cpu_dev,
+ "SoC ID %u is not part of IPQ8074 family, limiting to 1.4GHz!\n",
+ msm_id);
+ drv->versions = BIT(IPQ8074_ACORN_VERSION);
+ break;
+ }
+
+ return 0;
+}
+
static const struct qcom_cpufreq_match_data match_data_kryo = {
.get_version = qcom_cpufreq_kryo_name_version,
};
@@ -217,6 +260,10 @@ static const struct qcom_cpufreq_match_data match_data_qcs404 = {
.genpd_names = qcs404_genpd_names,
};
+static const struct qcom_cpufreq_match_data match_data_ipq8074 = {
+ .get_version = qcom_cpufreq_ipq8074_name_version,
+};
+
static int qcom_cpufreq_probe(struct platform_device *pdev)
{
struct qcom_cpufreq_drv *drv;
@@ -360,6 +407,7 @@ static const struct of_device_id qcom_cpufreq_match_list[] __initconst = {
{ .compatible = "qcom,msm8996", .data = &match_data_kryo },
{ .compatible = "qcom,qcs404", .data = &match_data_qcs404 },
{ .compatible = "qcom,ipq8064", .data = &match_data_krait },
+ { .compatible = "qcom,ipq8074", .data = &match_data_ipq8074 },
{ .compatible = "qcom,apq8064", .data = &match_data_krait },
{ .compatible = "qcom,msm8974", .data = &match_data_krait },
{ .compatible = "qcom,msm8960", .data = &match_data_krait },
--
2.41.0
From: Christian Marangi <[email protected]>
Add CPU OPP table for IPQ8062, IPQ8064 and IPQ8065 SoC.
Use opp-supported-hw binding to correctly enable and disable the
frequency as IPQ8062 supports up to 1.0Ghz, IPQ8064 supports up to
1.4GHz with 1.2GHz as an additional frequency and IPQ8065 supports
1.7GHZ but doesn't have 1.2GHZ frequency and has to be disabled.
Signed-off-by: Christian Marangi <[email protected]>
---
arch/arm/boot/dts/qcom/qcom-ipq8062.dtsi | 30 +++++++++++
arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi | 67 ++++++++++++++++++++++++
arch/arm/boot/dts/qcom/qcom-ipq8065.dtsi | 65 +++++++++++++++++++++++
3 files changed, 162 insertions(+)
diff --git a/arch/arm/boot/dts/qcom/qcom-ipq8062.dtsi b/arch/arm/boot/dts/qcom/qcom-ipq8062.dtsi
index 5d3ebd3e2e51..72d9782c3d6f 100644
--- a/arch/arm/boot/dts/qcom/qcom-ipq8062.dtsi
+++ b/arch/arm/boot/dts/qcom/qcom-ipq8062.dtsi
@@ -6,3 +6,33 @@ / {
model = "Qualcomm Technologies, Inc. IPQ8062";
compatible = "qcom,ipq8062", "qcom,ipq8064";
};
+
+&opp_table_cpu {
+ opp-384000000 {
+ opp-microvolt-speed0-pvs0 = <1000000 950000 1050000>;
+ opp-microvolt-speed0-pvs1 = <925000 878750 971250>;
+ opp-microvolt-speed0-pvs2 = <875000 831250 918750>;
+ opp-microvolt-speed0-pvs3 = <800000 760000 840000>;
+ };
+
+ opp-600000000 {
+ opp-microvolt-speed0-pvs0 = <1050000 997500 1102500>;
+ opp-microvolt-speed0-pvs1 = <975000 926250 1023750>;
+ opp-microvolt-speed0-pvs2 = <925000 878750 971250>;
+ opp-microvolt-speed0-pvs3 = <850000 807500 892500>;
+ };
+
+ opp-800000000 {
+ opp-microvolt-speed0-pvs0 = <1100000 1045000 1155000>;
+ opp-microvolt-speed0-pvs1 = <1025000 973750 1076250>;
+ opp-microvolt-speed0-pvs2 = <995000 945250 1044750>;
+ opp-microvolt-speed0-pvs3 = <900000 855000 945000>;
+ };
+
+ opp-1000000000 {
+ opp-microvolt-speed0-pvs0 = <1150000 1092500 1207500>;
+ opp-microvolt-speed0-pvs1 = <1075000 1021250 1128750>;
+ opp-microvolt-speed0-pvs2 = <1025000 973750 1076250>;
+ opp-microvolt-speed0-pvs3 = <950000 902500 997500>;
+ };
+};
diff --git a/arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi
index 6198f42f6a9c..cbbd28b43dc4 100644
--- a/arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi
+++ b/arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi
@@ -30,6 +30,7 @@ cpu0: cpu@0 {
next-level-cache = <&L2>;
qcom,acc = <&acc0>;
qcom,saw = <&saw0>;
+ operating-points-v2 = <&opp_table_cpu>;
};
cpu1: cpu@1 {
@@ -40,6 +41,7 @@ cpu1: cpu@1 {
next-level-cache = <&L2>;
qcom,acc = <&acc1>;
qcom,saw = <&saw1>;
+ operating-points-v2 = <&opp_table_cpu>;
};
L2: l2-cache {
@@ -49,6 +51,71 @@ L2: l2-cache {
};
};
+ opp_table_cpu: opp-table-cpu {
+ compatible = "operating-points-v2-kryo-cpu";
+ nvmem-cells = <&speedbin_efuse>;
+
+ opp-384000000 {
+ opp-hz = /bits/ 64 <384000000>;
+ opp-microvolt-speed0-pvs0 = <1000000 950000 1050000>;
+ opp-microvolt-speed0-pvs1 = <925000 878750 971250>;
+ opp-microvolt-speed0-pvs2 = <875000 831250 918750>;
+ opp-microvolt-speed0-pvs3 = <800000 760000 840000>;
+ opp-supported-hw = <0x7>;
+ clock-latency-ns = <100000>;
+ };
+
+ opp-600000000 {
+ opp-hz = /bits/ 64 <600000000>;
+ opp-microvolt-speed0-pvs0 = <1050000 997500 1102500>;
+ opp-microvolt-speed0-pvs1 = <975000 926250 1023750>;
+ opp-microvolt-speed0-pvs2 = <925000 878750 971250>;
+ opp-microvolt-speed0-pvs3 = <850000 807500 892500>;
+ opp-supported-hw = <0x7>;
+ clock-latency-ns = <100000>;
+ };
+
+ opp-800000000 {
+ opp-hz = /bits/ 64 <800000000>;
+ opp-microvolt-speed0-pvs0 = <1100000 1045000 1155000>;
+ opp-microvolt-speed0-pvs1 = <1025000 973750 1076250>;
+ opp-microvolt-speed0-pvs2 = <995000 945250 1044750>;
+ opp-microvolt-speed0-pvs3 = <900000 855000 945000>;
+ opp-supported-hw = <0x7>;
+ clock-latency-ns = <100000>;
+ };
+
+ opp-1000000000 {
+ opp-hz = /bits/ 64 <1000000000>;
+ opp-microvolt-speed0-pvs0 = <1150000 1092500 1207500>;
+ opp-microvolt-speed0-pvs1 = <1075000 1021250 1128750>;
+ opp-microvolt-speed0-pvs2 = <1025000 973750 1076250>;
+ opp-microvolt-speed0-pvs3 = <950000 902500 997500>;
+ opp-supported-hw = <0x7>;
+ clock-latency-ns = <100000>;
+ };
+
+ opp-1200000000 {
+ opp-hz = /bits/ 64 <1200000000>;
+ opp-microvolt-speed0-pvs0 = <1200000 1140000 1260000>;
+ opp-microvolt-speed0-pvs1 = <1125000 1068750 1181250>;
+ opp-microvolt-speed0-pvs2 = <1075000 1021250 1128750>;
+ opp-microvolt-speed0-pvs3 = <1000000 950000 1050000>;
+ opp-supported-hw = <0x2>;
+ clock-latency-ns = <100000>;
+ };
+
+ opp-1400000000 {
+ opp-hz = /bits/ 64 <1400000000>;
+ opp-microvolt-speed0-pvs0 = <1250000 1187500 1312500>;
+ opp-microvolt-speed0-pvs1 = <1175000 1116250 1233750>;
+ opp-microvolt-speed0-pvs2 = <1125000 1068750 1181250>;
+ opp-microvolt-speed0-pvs3 = <1050000 997500 1102500>;
+ opp-supported-hw = <0x6>;
+ clock-latency-ns = <100000>;
+ };
+ };
+
thermal-zones {
sensor0-thermal {
polling-delay-passive = <0>;
diff --git a/arch/arm/boot/dts/qcom/qcom-ipq8065.dtsi b/arch/arm/boot/dts/qcom/qcom-ipq8065.dtsi
index ea49f6cc416d..d9ead31b897b 100644
--- a/arch/arm/boot/dts/qcom/qcom-ipq8065.dtsi
+++ b/arch/arm/boot/dts/qcom/qcom-ipq8065.dtsi
@@ -6,3 +6,68 @@ / {
model = "Qualcomm Technologies, Inc. IPQ8065";
compatible = "qcom,ipq8065", "qcom,ipq8064";
};
+
+&opp_table_cpu {
+ opp-384000000 {
+ opp-microvolt-speed0-pvs0 = <975000 926250 1023750>;
+ opp-microvolt-speed0-pvs1 = <950000 902500 997500>;
+ opp-microvolt-speed0-pvs2 = <925000 878750 971250>;
+ opp-microvolt-speed0-pvs3 = <900000 855000 945000>;
+ opp-microvolt-speed0-pvs4 = <875000 831250 918750>;
+ opp-microvolt-speed0-pvs5 = <825000 783750 866250>;
+ opp-microvolt-speed0-pvs6 = <775000 736250 813750>;
+ };
+
+ opp-600000000 {
+ opp-microvolt-speed0-pvs0 = <1000000 950000 1050000>;
+ opp-microvolt-speed0-pvs1 = <975000 926250 1023750>;
+ opp-microvolt-speed0-pvs2 = <950000 902500 997500>;
+ opp-microvolt-speed0-pvs3 = <925000 878750 971250>;
+ opp-microvolt-speed0-pvs4 = <900000 855000 945000>;
+ opp-microvolt-speed0-pvs5 = <850000 807500 892500>;
+ opp-microvolt-speed0-pvs6 = <800000 760000 840000>;
+ };
+
+ opp-800000000 {
+ opp-microvolt-speed0-pvs0 = <1050000 997500 1102500>;
+ opp-microvolt-speed0-pvs1 = <1025000 973750 1076250>;
+ opp-microvolt-speed0-pvs2 = <1000000 950000 1050000>;
+ opp-microvolt-speed0-pvs3 = <975000 926250 1023750>;
+ opp-microvolt-speed0-pvs4 = <950000 902500 997500>;
+ opp-microvolt-speed0-pvs5 = <900000 855000 945000>;
+ opp-microvolt-speed0-pvs6 = <850000 807500 892500>;
+ };
+
+ opp-1000000000 {
+ opp-microvolt-speed0-pvs0 = <1100000 1045000 1155000>;
+ opp-microvolt-speed0-pvs1 = <1075000 1021250 1128750>;
+ opp-microvolt-speed0-pvs2 = <1050000 997500 1102500>;
+ opp-microvolt-speed0-pvs3 = <1025000 973750 1076250>;
+ opp-microvolt-speed0-pvs4 = <1000000 950000 1050000>;
+ opp-microvolt-speed0-pvs5 = <950000 902500 997500>;
+ opp-microvolt-speed0-pvs6 = <900000 855000 945000>;
+ };
+
+ opp-1400000000 {
+ opp-microvolt-speed4-pvs0 = <1175000 1116250 1233750>;
+ opp-microvolt-speed4-pvs1 = <1150000 1092500 1207500>;
+ opp-microvolt-speed4-pvs2 = <1125000 1068750 1181250>;
+ opp-microvolt-speed4-pvs3 = <1100000 1045000 1155000>;
+ opp-microvolt-speed4-pvs4 = <1075000 1021250 1128750>;
+ opp-microvolt-speed4-pvs5 = <1025000 973750 1076250>;
+ opp-microvolt-speed4-pvs6 = <975000 926250 1023750>;
+ };
+
+ opp-1725000000 {
+ opp-hz = /bits/ 64 <1725000000>;
+ opp-microvolt-speed0-pvs0 = <1262500 1199375 1325625>;
+ opp-microvolt-speed0-pvs1 = <1225000 1163750 1286250>;
+ opp-microvolt-speed0-pvs2 = <1200000 1140000 1260000>;
+ opp-microvolt-speed0-pvs3 = <1175000 1116250 1233750>;
+ opp-microvolt-speed0-pvs4 = <1150000 1092500 1207500>;
+ opp-microvolt-speed0-pvs5 = <1100000 1045000 1155000>;
+ opp-microvolt-speed0-pvs6 = <1050000 997500 1102500>;
+ opp-supported-hw = <0x4>;
+ clock-latency-ns = <100000>;
+ };
+};
--
2.41.0
On Fri, 29 Sept 2023 at 15:57, Konrad Dybcio <[email protected]> wrote:
>
> On 28.09.2023 23:04, Robert Marko wrote:
> > From: Christian Marangi <[email protected]>
> >
> > Add CPU OPP table for IPQ8062, IPQ8064 and IPQ8065 SoC.
> > Use opp-supported-hw binding to correctly enable and disable the
> > frequency as IPQ8062 supports up to 1.0Ghz, IPQ8064 supports up to
> > 1.4GHz with 1.2GHz as an additional frequency and IPQ8065 supports
> > 1.7GHZ but doesn't have 1.2GHZ frequency and has to be disabled.
> >
> > Signed-off-by: Christian Marangi <[email protected]>
> > ---
> When resending somebody else's patches, you need to add your own
> sign-off at the end.
Yes, I spotted it only after sending and it did not make sense to
resend immediately it.
Will be part of v5 that has DT bindings sorted out.
Regards,
Robert
>
> Konrad
On 28.09.2023 23:04, Robert Marko wrote:
> From: Christian Marangi <[email protected]>
>
> Add CPU OPP table for IPQ8062, IPQ8064 and IPQ8065 SoC.
> Use opp-supported-hw binding to correctly enable and disable the
> frequency as IPQ8062 supports up to 1.0Ghz, IPQ8064 supports up to
> 1.4GHz with 1.2GHz as an additional frequency and IPQ8065 supports
> 1.7GHZ but doesn't have 1.2GHZ frequency and has to be disabled.
>
> Signed-off-by: Christian Marangi <[email protected]>
> ---
When resending somebody else's patches, you need to add your own
sign-off at the end.
Konrad