2023-09-28 23:02:01

by Robert Marko

[permalink] [raw]
Subject: [PATCH 1/2] dt-bindings: clocks: qcom,gcc-ipq8074: allow QMP PCI PHY PIPE clocks

Allow passing QMP PCI PHY PIPE clocks to the IPQ8074 GCC to avoid having
to do a global matching by name.

Signed-off-by: Robert Marko <[email protected]>
---
Documentation/devicetree/bindings/clock/qcom,gcc-ipq8074.yaml | 4 ++++
1 file changed, 4 insertions(+)

diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-ipq8074.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-ipq8074.yaml
index 52e7831a8d6d..2d44ddc45aab 100644
--- a/Documentation/devicetree/bindings/clock/qcom,gcc-ipq8074.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,gcc-ipq8074.yaml
@@ -27,11 +27,15 @@ properties:
items:
- description: board XO clock
- description: sleep clock
+ - description: Gen3 QMP PCIe PHY PIPE clock
+ - description: Gen2 QMP PCIe PHY PIPE clock

clock-names:
items:
- const: xo
- const: sleep_clk
+ - const: pcie0_pipe
+ - const: pcie1_pipe

required:
- compatible
--
2.41.0


2023-09-30 10:37:22

by Robert Marko

[permalink] [raw]
Subject: [PATCH 2/2] arm64: dts: qcom: ipq8074: pass QMP PCI PHY PIPE clocks to GCC

Pass QMP PCI PHY PIPE clocks to the GCC controller so it does not have to
find them by matching globaly by name.

If not passed directly, driver maintains backwards compatibility by then
falling back to global lookup.

Signed-off-by: Robert Marko <[email protected]>
---
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
index 643b586c0dec..1f108ee2e8ba 100644
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -407,8 +407,8 @@ qpic_pins: qpic-state {
gcc: gcc@1800000 {
compatible = "qcom,gcc-ipq8074";
reg = <0x01800000 0x80000>;
- clocks = <&xo>, <&sleep_clk>;
- clock-names = "xo", "sleep_clk";
+ clocks = <&xo>, <&sleep_clk>, <&pcie_qmp0>, <&pcie_qmp1>;
+ clock-names = "xo", "sleep_clk", "pcie0_pipe", "pcie1_pipe";
#clock-cells = <1>;
#power-domain-cells = <1>;
#reset-cells = <1>;
--
2.41.0