This series add base description of UART, TLMM, RPMHCC, GCC and RPMh PD
nodes which helps SM4450 boot to shell with console on boards with this
SoC.
Signed-off-by: Tengfei Fan <[email protected]>
---
Resend this patch series for get more review.
This patch series depends on below patch series:
"[PATCH v2 0/4] clk: qcom: Add support for GCC and RPMHCC on SM4450"
https://lore.kernel.org/linux-arm-msm/[email protected]/
"[PATCH v4 0/2] pinctl: qcom: Add SM4450 pinctrl driver"
https://lore.kernel.org/linux-arm-msm/[email protected]/
v4 -> v5:
- separate reserved gpios setting from enable UART console patch
v3 -> v4:
- adjustment the sequence of property and property-names
- update 0 to 0x0 for reg params
- remove unrelated change
- separate SoC change and board change
v2 -> v3:
- fix dtbs_check warning
- remove interconnect, iommu, scm and tcsr related code
- rearrangement dt node
- remove smmu, scm and tcsr related documentation update
- enable CONFIG_SM_GCC_4450 in defconfig related patch
v1 -> v2:
- setting "qcom,rpmh-rsc" compatible to the first property
- keep order by unit address
- move tlmm node into soc node
- update arm,smmu.yaml
- add enable pinctrl and interconnect defconfig patches
- remove blank line
- redo dtbs_check check
previous discussion here:
[1] v4: https://lore.kernel.org/linux-arm-msm/[email protected]
[2] v3: https://lore.kernel.org/linux-arm-msm/[email protected]
[3] v2: https://lore.kernel.org/linux-arm-msm/[email protected]
[4] v1: https://lore.kernel.org/linux-arm-msm/[email protected]
Ajit Pandey (1):
arm64: dts: qcom: sm4450: Add apps_rsc and cmd_db node
Tengfei Fan (6):
dt-bindings: interrupt-controller: qcom,pdc: document qcom,sm4450-pdc
arm64: dts: qcom: sm4450: Add RPMH and Global clock
arm64: dts: qcom: add uart console support for SM4450
arm64: dts: qcom: sm4450-qrd: add QRD4450 uart support
arm64: dts: qcom: sm4450-qrd: mark QRD4450 reserved gpios
arm64: defconfig: enable clock controller and pinctrl
.../interrupt-controller/qcom,pdc.yaml | 1 +
arch/arm64/boot/dts/qcom/sm4450-qrd.dts | 19 +++-
arch/arm64/boot/dts/qcom/sm4450.dtsi | 107 ++++++++++++++++++
arch/arm64/configs/defconfig | 2 +
4 files changed, 127 insertions(+), 2 deletions(-)
base-commit: 940fcc189c51032dd0282cbee4497542c982ac59
--
2.17.1
From: Ajit Pandey <[email protected]>
Add apps_rsc node and cmd_db memory region for sm4450.
Reviewed-by: Konrad Dybcio <[email protected]>
Signed-off-by: Ajit Pandey <[email protected]>
Signed-off-by: Tengfei Fan <[email protected]>
---
arch/arm64/boot/dts/qcom/sm4450.dtsi | 35 ++++++++++++++++++++++++++++
1 file changed, 35 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm4450.dtsi b/arch/arm64/boot/dts/qcom/sm4450.dtsi
index c4e5b33f5169..5e09880f4218 100644
--- a/arch/arm64/boot/dts/qcom/sm4450.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm4450.dtsi
@@ -5,6 +5,7 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/soc/qcom,rpmh-rsc.h>
/ {
interrupt-parent = <&intc>;
@@ -328,6 +329,18 @@
};
};
+ reserved_memory: reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ aop_cmd_db_mem: cmd-db@80860000 {
+ compatible = "qcom,cmd-db";
+ reg = <0x0 0x80860000 0x0 0x20000>;
+ no-map;
+ };
+ };
+
soc: soc@0 {
#address-cells = <2>;
#size-cells = <2>;
@@ -419,6 +432,28 @@
status = "disabled";
};
};
+
+ apps_rsc: rsc@17a00000 {
+ compatible = "qcom,rpmh-rsc";
+ reg = <0x0 0x17a00000 0x0 0x10000>,
+ <0x0 0x17a10000 0x0 0x10000>,
+ <0x0 0x17a20000 0x0 0x10000>;
+ reg-names = "drv-0", "drv-1", "drv-2";
+ interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+ label = "apps_rsc";
+ qcom,tcs-offset = <0xd00>;
+ qcom,drv-id = <2>;
+ qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>,
+ <WAKE_TCS 3>, <CONTROL_TCS 0>;
+ power-domains = <&CLUSTER_PD>;
+
+ apps_bcm_voter: bcm-voter {
+ compatible = "qcom,bcm-voter";
+ };
+ };
+
};
timer {
--
2.17.1
Add device node for RPMH and Global clock controller on Qualcomm
SM4450 platform.
Reviewed-by: Konrad Dybcio <[email protected]>
Signed-off-by: Ajit Pandey <[email protected]>
Signed-off-by: Tengfei Fan <[email protected]>
---
arch/arm64/boot/dts/qcom/sm4450.dtsi | 23 +++++++++++++++++++++++
1 file changed, 23 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm4450.dtsi b/arch/arm64/boot/dts/qcom/sm4450.dtsi
index 5e09880f4218..5a8a54b0f6c1 100644
--- a/arch/arm64/boot/dts/qcom/sm4450.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm4450.dtsi
@@ -3,6 +3,8 @@
* Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
*/
+#include <dt-bindings/clock/qcom,rpmh.h>
+#include <dt-bindings/clock/qcom,sm4450-gcc.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
@@ -348,6 +350,20 @@
dma-ranges = <0 0 0 0 0x10 0>;
compatible = "simple-bus";
+ gcc: clock-controller@100000 {
+ compatible = "qcom,sm4450-gcc";
+ reg = <0x0 0x00100000 0x0 0x1f4200>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ clocks = <&rpmhcc RPMH_CXO_CLK>,
+ <&sleep_clk>,
+ <0>,
+ <0>,
+ <0>,
+ <0>;
+ };
+
tcsr_mutex: hwlock@1f40000 {
compatible = "qcom,tcsr-mutex";
reg = <0x0 0x01f40000 0x0 0x40000>;
@@ -452,6 +468,13 @@
apps_bcm_voter: bcm-voter {
compatible = "qcom,bcm-voter";
};
+
+ rpmhcc: clock-controller {
+ compatible = "qcom,sm4450-rpmh-clk";
+ #clock-cells = <1>;
+ clocks = <&xo_board>;
+ clock-names = "xo";
+ };
};
};
--
2.17.1
Add uart support for QRD4450 for enable uart console.
Reviewed-by: Konrad Dybcio <[email protected]>
Signed-off-by: Tengfei Fan <[email protected]>
---
arch/arm64/boot/dts/qcom/sm4450-qrd.dts | 14 ++++++++++++--
1 file changed, 12 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sm4450-qrd.dts b/arch/arm64/boot/dts/qcom/sm4450-qrd.dts
index 00a1c81ca397..bb8c58fb4267 100644
--- a/arch/arm64/boot/dts/qcom/sm4450-qrd.dts
+++ b/arch/arm64/boot/dts/qcom/sm4450-qrd.dts
@@ -10,9 +10,19 @@
model = "Qualcomm Technologies, Inc. SM4450 QRD";
compatible = "qcom,sm4450-qrd", "qcom,sm4450";
- aliases { };
+ aliases {
+ serial0 = &uart7;
+ };
chosen {
- bootargs = "console=hvc0";
+ stdout-path = "serial0:115200n8";
};
};
+
+&qupv3_id_0 {
+ status = "okay";
+};
+
+&uart7 {
+ status = "okay";
+};
--
2.17.1
Enable global clock controller and pinctrl for support the Qualcomm
SM4450 platform to boot to UART console.
The serial engine depends on some global clock controller and pinctrl, but
as the serial console driver is only available as built-in, so the global
clock controller and pinctrl also needs be built-in for the UART device to
probe and register the console.
Signed-off-by: Tengfei Fan <[email protected]>
---
arch/arm64/configs/defconfig | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 5f77f5d1fe94..c645ad738c72 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -598,6 +598,7 @@ CONFIG_PINCTRL_SC8280XP=y
CONFIG_PINCTRL_SDM660=y
CONFIG_PINCTRL_SDM670=y
CONFIG_PINCTRL_SDM845=y
+CONFIG_PINCTRL_SM4450=y
CONFIG_PINCTRL_SM6115=y
CONFIG_PINCTRL_SM6115_LPASS_LPI=m
CONFIG_PINCTRL_SM6125=y
@@ -1244,6 +1245,7 @@ CONFIG_SM_DISPCC_6115=m
CONFIG_SM_DISPCC_8250=y
CONFIG_SM_DISPCC_8450=m
CONFIG_SM_DISPCC_8550=m
+CONFIG_SM_GCC_4450=y
CONFIG_SM_GCC_6115=y
CONFIG_SM_GCC_8350=y
CONFIG_SM_GCC_8450=y
--
2.17.1
Hi Tengfei,
kernel test robot noticed the following build errors:
[auto build test ERROR on 940fcc189c51032dd0282cbee4497542c982ac59]
url: https://github.com/intel-lab-lkp/linux/commits/Tengfei-Fan/dt-bindings-interrupt-controller-qcom-pdc-document-qcom-sm4450-pdc/20231011-111816
base: 940fcc189c51032dd0282cbee4497542c982ac59
patch link: https://lore.kernel.org/r/20231011031415.3360-4-quic_tengfan%40quicinc.com
patch subject: [PATCH v5 RESEND 3/7] arm64: dts: qcom: sm4450: Add RPMH and Global clock
config: arm64-randconfig-003-20231014 (https://download.01.org/0day-ci/archive/20231014/[email protected]/config)
compiler: aarch64-linux-gcc (GCC) 13.2.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20231014/[email protected]/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <[email protected]>
| Closes: https://lore.kernel.org/oe-kbuild-all/[email protected]/
All errors (new ones prefixed by >>):
In file included from arch/arm64/boot/dts/qcom/sm4450-qrd.dts:8:
>> arch/arm64/boot/dts/qcom/sm4450.dtsi:7:10: fatal error: dt-bindings/clock/qcom,sm4450-gcc.h: No such file or directory
7 | #include <dt-bindings/clock/qcom,sm4450-gcc.h>
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
compilation terminated.
vim +7 arch/arm64/boot/dts/qcom/sm4450.dtsi
> 7 #include <dt-bindings/clock/qcom,sm4450-gcc.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
11
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki