Add base description of UART and TLMM nodes which helps SM4450
boot to shell with console on boards with this SoC.
Signed-off-by: Tengfei Fan <[email protected]>
---
arch/arm64/boot/dts/qcom/sm4450.dtsi | 49 ++++++++++++++++++++++++++++
1 file changed, 49 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm4450.dtsi b/arch/arm64/boot/dts/qcom/sm4450.dtsi
index 5a8a54b0f6c1..3e7ae3bebbe0 100644
--- a/arch/arm64/boot/dts/qcom/sm4450.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm4450.dtsi
@@ -364,6 +364,29 @@
<0>;
};
+ qupv3_id_0: geniqup@ac0000 {
+ compatible = "qcom,geni-se-qup";
+ reg = <0x0 0x00ac0000 0x0 0x2000>;
+ ranges;
+ clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
+ <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
+ clock-names = "m-ahb", "s-ahb";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ status = "disabled";
+
+ uart7: serial@a88000 {
+ compatible = "qcom,geni-debug-uart";
+ reg = <0x0 0x00a88000 0x0 0x4000>;
+ clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
+ clock-names = "se";
+ interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-0 = <&qup_uart7_tx>, <&qup_uart7_rx>;
+ pinctrl-names = "default";
+ status = "disabled";
+ };
+ };
+
tcsr_mutex: hwlock@1f40000 {
compatible = "qcom,tcsr-mutex";
reg = <0x0 0x01f40000 0x0 0x40000>;
@@ -380,6 +403,32 @@
interrupt-controller;
};
+ tlmm: pinctrl@f100000 {
+ compatible = "qcom,sm4450-tlmm";
+ reg = <0x0 0x0f100000 0x0 0x300000>;
+ interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ gpio-ranges = <&tlmm 0 0 137>;
+ wakeup-parent = <&pdc>;
+
+ qup_uart7_rx: qup-uart7-rx-state {
+ pins = "gpio23";
+ function = "qup1_se2_l2";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ qup_uart7_tx: qup-uart7-tx-state {
+ pins = "gpio22";
+ function = "qup1_se2_l2";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+
intc: interrupt-controller@17200000 {
compatible = "arm,gic-v3";
reg = <0x0 0x17200000 0x0 0x10000>, /* GICD */
--
2.17.1