2023-10-12 17:21:57

by Manivannan Sadhasivam

[permalink] [raw]
Subject: [PATCH v7 0/5] UFS: Add OPP support

Hi,

This series adds OPP (Operating Points) support to UFSHCD driver.

Motivation behind adding OPP support is to scale both clocks as well as
regulators/performance state dynamically. Currently, UFSHCD just scales
clock frequency during runtime with the help of "freq-table-hz" property
defined in devicetree. With the addition of OPP tables in devicetree (as
done for Qcom SDM845 and SM8250 SoCs in this series) UFSHCD can now scale
both clocks and performance state of power domain which helps in power
saving.

For the addition of OPP support to UFSHCD, there are changes required to
the OPP framework and devfreq drivers. The OPP framework changes are already
merged and the devfreq change is added in this series.

Credits
=======

This series is a continuation of previous work by Krzysztof Kozlowski [1].

Testing
=======

This series is tested on 96Boards RB3 (SDM845 SoC) and RB5 (SM8250 SoC)
development boards.

Merging Strategy
================

Since the devfreq patch got an Ack from the maintainer, either it can be merged
to scsi tree with rest of the patches or merged separately through devfreq tree.

Thanks,
Mani

[1] https://lore.kernel.org/all/[email protected]/

Changes in v7:

* Added missing EXPORT_SYMBOL_GPL() for ufshcd_opp_config_clks() API as reported
by Alessandro Carminati

Changes in v6:

* Collected tags from Dmitry
* Fixed bindings issues reported by Krzysztof

Changes in v5:

* Dropped the devfreq patch since it got applied
* Fixed the bindings issue reported by DT bot
* Rebased on top of mkp/scsi/for-next

Changes in v4:

* Rebased on top of v6.6-rc3

Changes in v3:

* Rebased on top of linux-next/master tag: next-20230731
* Dropped the already applied patches (dts, opp binding and framework)
* Moved the interconnect patches to a separate series:
https://lore.kernel.org/linux-scsi/[email protected]/
* Moved ufshcd_opp_config_clks() API to ufshcd.c to fix the build failure
reported by Kbuild bot: https://lore.kernel.org/all/[email protected]/
* Collected Acks
* v2: https://lore.kernel.org/all/[email protected]/

Changes in v2:

* Added more description to the bindings patch 2/15
* Fixed dev_pm_opp_put() usage in patch 10/15
* Added a new patch for adding enums for UFS lanes 14/15
* Changed the icc variables to mem_bw and cfg_bw and used
the enums for gears and lanes in bw_table
* Collected review tags
* Added SCSI list and folks
* Removed duplicate patches

Krzysztof Kozlowski (2):
dt-bindings: ufs: common: add OPP table
arm64: dts: qcom: sdm845: Add OPP table support to UFSHC

Manivannan Sadhasivam (3):
scsi: ufs: core: Add OPP support for scaling clocks and regulators
scsi: ufs: host: Add support for parsing OPP
arm64: dts: qcom: sm8250: Add OPP table support to UFSHC

.../devicetree/bindings/ufs/ufs-common.yaml | 35 +++-
arch/arm64/boot/dts/qcom/sdm845.dtsi | 42 +++-
arch/arm64/boot/dts/qcom/sm8250.dtsi | 39 +++-
drivers/ufs/core/ufshcd.c | 180 ++++++++++++++----
drivers/ufs/host/ufshcd-pltfrm.c | 78 ++++++++
include/ufs/ufshcd.h | 7 +
6 files changed, 326 insertions(+), 55 deletions(-)

--
2.25.1


2023-10-12 17:22:45

by Manivannan Sadhasivam

[permalink] [raw]
Subject: [PATCH v7 1/5] dt-bindings: ufs: common: add OPP table

From: Krzysztof Kozlowski <[email protected]>

Except scaling UFS and bus clocks, it's necessary to scale also the
voltages of regulators or power domain performance state levels. Adding
Operating Performance Points table allows to adjust power domain
performance state, depending on the UFS clock speed.

OPPv2 deprecates previous property limited to clock scaling:
freq-table-hz.

Signed-off-by: Krzysztof Kozlowski <[email protected]>
Reviewed-by: Rob Herring <[email protected]>
Signed-off-by: Manivannan Sadhasivam <[email protected]>
---
.../devicetree/bindings/ufs/ufs-common.yaml | 35 +++++++++++++++++--
1 file changed, 32 insertions(+), 3 deletions(-)

diff --git a/Documentation/devicetree/bindings/ufs/ufs-common.yaml b/Documentation/devicetree/bindings/ufs/ufs-common.yaml
index bbaee4f5f7b2..985ea8f64de8 100644
--- a/Documentation/devicetree/bindings/ufs/ufs-common.yaml
+++ b/Documentation/devicetree/bindings/ufs/ufs-common.yaml
@@ -20,11 +20,25 @@ properties:
items:
- description: Minimum frequency for given clock in Hz
- description: Maximum frequency for given clock in Hz
+ deprecated: true
description: |
+ Preferred is operating-points-v2.
+
Array of <min max> operating frequencies in Hz stored in the same order
- as the clocks property. If this property is not defined or a value in the
- array is "0" then it is assumed that the frequency is set by the parent
- clock or a fixed rate clock source.
+ as the clocks property. If either this property or operating-points-v2 is
+ not defined or a value in the array is "0" then it is assumed that the
+ frequency is set by the parent clock or a fixed rate clock source.
+
+ operating-points-v2:
+ description:
+ Preferred over freq-table-hz.
+ If present, each OPP must contain array of frequencies stored in the same
+ order for each clock. If clock frequency in the array is "0" then it is
+ assumed that the frequency is set by the parent clock or a fixed rate
+ clock source.
+
+ opp-table:
+ type: object

interrupts:
maxItems: 1
@@ -75,8 +89,23 @@ properties:

dependencies:
freq-table-hz: [ clocks ]
+ operating-points-v2: [ clocks, clock-names ]

required:
- interrupts

+allOf:
+ - if:
+ required:
+ - freq-table-hz
+ then:
+ properties:
+ operating-points-v2: false
+ - if:
+ required:
+ - operating-points-v2
+ then:
+ properties:
+ freq-table-hz: false
+
additionalProperties: true
--
2.25.1

2023-10-12 17:23:15

by Manivannan Sadhasivam

[permalink] [raw]
Subject: [PATCH v7 2/5] scsi: ufs: core: Add OPP support for scaling clocks and regulators

UFS core is only scaling the clocks during devfreq scaling and
initialization. But for an optimum power saving, regulators should also
be scaled along with the clocks.

So let's use the OPP framework which supports scaling clocks, regulators,
and performance state using OPP table defined in devicetree. For
accomodating the OPP support, the existing APIs (ufshcd_scale_clks,
ufshcd_is_devfreq_scaling_required and ufshcd_devfreq_scale) are modified
to accept "freq" as an argument which in turn used by the OPP helpers.

The OPP support is added along with the old freq-table based clock scaling
so that the existing platforms work as expected.

Co-developed-by: Krzysztof Kozlowski <[email protected]>
Signed-off-by: Krzysztof Kozlowski <[email protected]>
Signed-off-by: Manivannan Sadhasivam <[email protected]>
---
drivers/ufs/core/ufshcd.c | 144 +++++++++++++++++++++++++++++---------
include/ufs/ufshcd.h | 4 ++
2 files changed, 115 insertions(+), 33 deletions(-)

diff --git a/drivers/ufs/core/ufshcd.c b/drivers/ufs/core/ufshcd.c
index c45737c5adb9..3f52e05002e4 100644
--- a/drivers/ufs/core/ufshcd.c
+++ b/drivers/ufs/core/ufshcd.c
@@ -20,6 +20,7 @@
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/module.h>
+#include <linux/pm_opp.h>
#include <linux/regulator/consumer.h>
#include <linux/sched/clock.h>
#include <linux/iopoll.h>
@@ -275,7 +276,8 @@ static int ufshcd_host_reset_and_restore(struct ufs_hba *hba);
static void ufshcd_resume_clkscaling(struct ufs_hba *hba);
static void ufshcd_suspend_clkscaling(struct ufs_hba *hba);
static void __ufshcd_suspend_clkscaling(struct ufs_hba *hba);
-static int ufshcd_scale_clks(struct ufs_hba *hba, bool scale_up);
+static int ufshcd_scale_clks(struct ufs_hba *hba, unsigned long freq,
+ bool scale_up);
static irqreturn_t ufshcd_intr(int irq, void *__hba);
static int ufshcd_change_power_mode(struct ufs_hba *hba,
struct ufs_pa_layer_attr *pwr_mode);
@@ -1062,14 +1064,32 @@ static int ufshcd_set_clk_freq(struct ufs_hba *hba, bool scale_up)
return ret;
}

+static int ufshcd_opp_set_rate(struct ufs_hba *hba, unsigned long freq)
+{
+ struct dev_pm_opp *opp;
+ int ret;
+
+ opp = dev_pm_opp_find_freq_floor_indexed(hba->dev,
+ &freq, 0);
+ if (IS_ERR(opp))
+ return PTR_ERR(opp);
+
+ ret = dev_pm_opp_set_opp(hba->dev, opp);
+ dev_pm_opp_put(opp);
+
+ return ret;
+}
+
/**
* ufshcd_scale_clks - scale up or scale down UFS controller clocks
* @hba: per adapter instance
+ * @freq: frequency to scale
* @scale_up: True if scaling up and false if scaling down
*
* Return: 0 if successful; < 0 upon failure.
*/
-static int ufshcd_scale_clks(struct ufs_hba *hba, bool scale_up)
+static int ufshcd_scale_clks(struct ufs_hba *hba, unsigned long freq,
+ bool scale_up)
{
int ret = 0;
ktime_t start = ktime_get();
@@ -1078,13 +1098,21 @@ static int ufshcd_scale_clks(struct ufs_hba *hba, bool scale_up)
if (ret)
goto out;

- ret = ufshcd_set_clk_freq(hba, scale_up);
+ if (hba->use_pm_opp)
+ ret = ufshcd_opp_set_rate(hba, freq);
+ else
+ ret = ufshcd_set_clk_freq(hba, scale_up);
if (ret)
goto out;

ret = ufshcd_vops_clk_scale_notify(hba, scale_up, POST_CHANGE);
- if (ret)
- ufshcd_set_clk_freq(hba, !scale_up);
+ if (ret) {
+ if (hba->use_pm_opp)
+ ufshcd_opp_set_rate(hba,
+ hba->devfreq->previous_freq);
+ else
+ ufshcd_set_clk_freq(hba, !scale_up);
+ }

out:
trace_ufshcd_profile_clk_scaling(dev_name(hba->dev),
@@ -1096,12 +1124,13 @@ static int ufshcd_scale_clks(struct ufs_hba *hba, bool scale_up)
/**
* ufshcd_is_devfreq_scaling_required - check if scaling is required or not
* @hba: per adapter instance
+ * @freq: frequency to scale
* @scale_up: True if scaling up and false if scaling down
*
* Return: true if scaling is required, false otherwise.
*/
static bool ufshcd_is_devfreq_scaling_required(struct ufs_hba *hba,
- bool scale_up)
+ unsigned long freq, bool scale_up)
{
struct ufs_clk_info *clki;
struct list_head *head = &hba->clk_list_head;
@@ -1109,6 +1138,9 @@ static bool ufshcd_is_devfreq_scaling_required(struct ufs_hba *hba,
if (list_empty(head))
return false;

+ if (hba->use_pm_opp)
+ return freq != hba->clk_scaling.target_freq;
+
list_for_each_entry(clki, head, list) {
if (!IS_ERR_OR_NULL(clki->clk)) {
if (scale_up && clki->max_freq) {
@@ -1304,12 +1336,14 @@ static void ufshcd_clock_scaling_unprepare(struct ufs_hba *hba, int err, bool sc
/**
* ufshcd_devfreq_scale - scale up/down UFS clocks and gear
* @hba: per adapter instance
+ * @freq: frequency to scale
* @scale_up: True for scaling up and false for scalin down
*
* Return: 0 for success; -EBUSY if scaling can't happen at this time; non-zero
* for any other errors.
*/
-static int ufshcd_devfreq_scale(struct ufs_hba *hba, bool scale_up)
+static int ufshcd_devfreq_scale(struct ufs_hba *hba, unsigned long freq,
+ bool scale_up)
{
int ret = 0;

@@ -1324,7 +1358,7 @@ static int ufshcd_devfreq_scale(struct ufs_hba *hba, bool scale_up)
goto out_unprepare;
}

- ret = ufshcd_scale_clks(hba, scale_up);
+ ret = ufshcd_scale_clks(hba, freq, scale_up);
if (ret) {
if (!scale_up)
ufshcd_scale_gear(hba, true);
@@ -1335,7 +1369,8 @@ static int ufshcd_devfreq_scale(struct ufs_hba *hba, bool scale_up)
if (scale_up) {
ret = ufshcd_scale_gear(hba, true);
if (ret) {
- ufshcd_scale_clks(hba, false);
+ ufshcd_scale_clks(hba, hba->devfreq->previous_freq,
+ false);
goto out_unprepare;
}
}
@@ -1393,9 +1428,22 @@ static int ufshcd_devfreq_target(struct device *dev,
if (!ufshcd_is_clkscaling_supported(hba))
return -EINVAL;

- clki = list_first_entry(&hba->clk_list_head, struct ufs_clk_info, list);
- /* Override with the closest supported frequency */
- *freq = (unsigned long) clk_round_rate(clki->clk, *freq);
+ if (hba->use_pm_opp) {
+ struct dev_pm_opp *opp;
+
+ /* Get the recommended frequency from OPP framework */
+ opp = devfreq_recommended_opp(dev, freq, flags);
+ if (IS_ERR(opp))
+ return PTR_ERR(opp);
+
+ dev_pm_opp_put(opp);
+ } else {
+ /* Override with the closest supported frequency */
+ clki = list_first_entry(&hba->clk_list_head, struct ufs_clk_info,
+ list);
+ *freq = (unsigned long) clk_round_rate(clki->clk, *freq);
+ }
+
spin_lock_irqsave(hba->host->host_lock, irq_flags);
if (ufshcd_eh_in_progress(hba)) {
spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
@@ -1410,12 +1458,17 @@ static int ufshcd_devfreq_target(struct device *dev,
goto out;
}

- /* Decide based on the rounded-off frequency and update */
- scale_up = *freq == clki->max_freq;
- if (!scale_up)
+ /* Decide based on the target or rounded-off frequency and update */
+ if (hba->use_pm_opp)
+ scale_up = *freq > hba->clk_scaling.target_freq;
+ else
+ scale_up = *freq == clki->max_freq;
+
+ if (!hba->use_pm_opp && !scale_up)
*freq = clki->min_freq;
+
/* Update the frequency */
- if (!ufshcd_is_devfreq_scaling_required(hba, scale_up)) {
+ if (!ufshcd_is_devfreq_scaling_required(hba, *freq, scale_up)) {
spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
ret = 0;
goto out; /* no state change required */
@@ -1423,7 +1476,9 @@ static int ufshcd_devfreq_target(struct device *dev,
spin_unlock_irqrestore(hba->host->host_lock, irq_flags);

start = ktime_get();
- ret = ufshcd_devfreq_scale(hba, scale_up);
+ ret = ufshcd_devfreq_scale(hba, *freq, scale_up);
+ if (!ret)
+ hba->clk_scaling.target_freq = *freq;

trace_ufshcd_profile_clk_scaling(dev_name(hba->dev),
(scale_up ? "up" : "down"),
@@ -1443,8 +1498,6 @@ static int ufshcd_devfreq_get_dev_status(struct device *dev,
struct ufs_hba *hba = dev_get_drvdata(dev);
struct ufs_clk_scaling *scaling = &hba->clk_scaling;
unsigned long flags;
- struct list_head *clk_list = &hba->clk_list_head;
- struct ufs_clk_info *clki;
ktime_t curr_t;

if (!ufshcd_is_clkscaling_supported(hba))
@@ -1457,17 +1510,24 @@ static int ufshcd_devfreq_get_dev_status(struct device *dev,
if (!scaling->window_start_t)
goto start_window;

- clki = list_first_entry(clk_list, struct ufs_clk_info, list);
/*
* If current frequency is 0, then the ondemand governor considers
* there's no initial frequency set. And it always requests to set
* to max. frequency.
*/
- stat->current_frequency = clki->curr_freq;
+ if (hba->use_pm_opp) {
+ stat->current_frequency = hba->clk_scaling.target_freq;
+ } else {
+ struct list_head *clk_list = &hba->clk_list_head;
+ struct ufs_clk_info *clki;
+
+ clki = list_first_entry(clk_list, struct ufs_clk_info, list);
+ stat->current_frequency = clki->curr_freq;
+ }
+
if (scaling->is_busy_started)
scaling->tot_busy_t += ktime_us_delta(curr_t,
scaling->busy_start_t);
-
stat->total_time = ktime_us_delta(curr_t, scaling->window_start_t);
stat->busy_time = scaling->tot_busy_t;
start_window:
@@ -1496,9 +1556,11 @@ static int ufshcd_devfreq_init(struct ufs_hba *hba)
if (list_empty(clk_list))
return 0;

- clki = list_first_entry(clk_list, struct ufs_clk_info, list);
- dev_pm_opp_add(hba->dev, clki->min_freq, 0);
- dev_pm_opp_add(hba->dev, clki->max_freq, 0);
+ if (!hba->use_pm_opp) {
+ clki = list_first_entry(clk_list, struct ufs_clk_info, list);
+ dev_pm_opp_add(hba->dev, clki->min_freq, 0);
+ dev_pm_opp_add(hba->dev, clki->max_freq, 0);
+ }

ufshcd_vops_config_scaling_param(hba, &hba->vps->devfreq_profile,
&hba->vps->ondemand_data);
@@ -1510,8 +1572,10 @@ static int ufshcd_devfreq_init(struct ufs_hba *hba)
ret = PTR_ERR(devfreq);
dev_err(hba->dev, "Unable to register with devfreq %d\n", ret);

- dev_pm_opp_remove(hba->dev, clki->min_freq);
- dev_pm_opp_remove(hba->dev, clki->max_freq);
+ if (!hba->use_pm_opp) {
+ dev_pm_opp_remove(hba->dev, clki->min_freq);
+ dev_pm_opp_remove(hba->dev, clki->max_freq);
+ }
return ret;
}

@@ -1523,7 +1587,6 @@ static int ufshcd_devfreq_init(struct ufs_hba *hba)
static void ufshcd_devfreq_remove(struct ufs_hba *hba)
{
struct list_head *clk_list = &hba->clk_list_head;
- struct ufs_clk_info *clki;

if (!hba->devfreq)
return;
@@ -1531,9 +1594,13 @@ static void ufshcd_devfreq_remove(struct ufs_hba *hba)
devfreq_remove_device(hba->devfreq);
hba->devfreq = NULL;

- clki = list_first_entry(clk_list, struct ufs_clk_info, list);
- dev_pm_opp_remove(hba->dev, clki->min_freq);
- dev_pm_opp_remove(hba->dev, clki->max_freq);
+ if (!hba->use_pm_opp) {
+ struct ufs_clk_info *clki;
+
+ clki = list_first_entry(clk_list, struct ufs_clk_info, list);
+ dev_pm_opp_remove(hba->dev, clki->min_freq);
+ dev_pm_opp_remove(hba->dev, clki->max_freq);
+ }
}

static void __ufshcd_suspend_clkscaling(struct ufs_hba *hba)
@@ -1618,7 +1685,7 @@ static ssize_t ufshcd_clkscale_enable_store(struct device *dev,
ufshcd_resume_clkscaling(hba);
} else {
ufshcd_suspend_clkscaling(hba);
- err = ufshcd_devfreq_scale(hba, true);
+ err = ufshcd_devfreq_scale(hba, ULONG_MAX, true);
if (err)
dev_err(hba->dev, "%s: failed to scale clocks up %d\n",
__func__, err);
@@ -7619,7 +7686,7 @@ static int ufshcd_host_reset_and_restore(struct ufs_hba *hba)
hba->silence_err_logs = false;

/* scale up clocks to max frequency before full reinitialization */
- ufshcd_scale_clks(hba, true);
+ ufshcd_scale_clks(hba, ULONG_MAX, true);

err = ufshcd_hba_enable(hba);

@@ -9165,6 +9232,17 @@ static int ufshcd_init_clocks(struct ufs_hba *hba)
dev_dbg(dev, "%s: clk: %s, rate: %lu\n", __func__,
clki->name, clk_get_rate(clki->clk));
}
+
+ /* Set Max. frequency for all clocks */
+ if (hba->use_pm_opp) {
+ ret = ufshcd_opp_set_rate(hba, ULONG_MAX);
+ if (ret) {
+ dev_err(hba->dev, "%s: failed to set OPP: %d", __func__,
+ ret);
+ goto out;
+ }
+ }
+
out:
return ret;
}
diff --git a/include/ufs/ufshcd.h b/include/ufs/ufshcd.h
index e0d6590d163d..fc0d6d37319a 100644
--- a/include/ufs/ufshcd.h
+++ b/include/ufs/ufshcd.h
@@ -429,6 +429,7 @@ struct ufs_clk_gating {
* @workq: workqueue to schedule devfreq suspend/resume work
* @suspend_work: worker to suspend devfreq
* @resume_work: worker to resume devfreq
+ * @target_freq: frequency requested by devfreq framework
* @min_gear: lowest HS gear to scale down to
* @is_enabled: tracks if scaling is currently enabled or not, controlled by
* clkscale_enable sysfs node
@@ -448,6 +449,7 @@ struct ufs_clk_scaling {
struct workqueue_struct *workq;
struct work_struct suspend_work;
struct work_struct resume_work;
+ unsigned long target_freq;
u32 min_gear;
bool is_enabled;
bool is_allowed;
@@ -862,6 +864,7 @@ enum ufshcd_mcq_opr {
* @auto_bkops_enabled: to track whether bkops is enabled in device
* @vreg_info: UFS device voltage regulator information
* @clk_list_head: UFS host controller clocks list node head
+ * @use_pm_opp: Indicates whether OPP based scaling is used or not
* @req_abort_count: number of times ufshcd_abort() has been called
* @lanes_per_direction: number of lanes per data direction between the UFS
* controller and the UFS device.
@@ -1012,6 +1015,7 @@ struct ufs_hba {
bool auto_bkops_enabled;
struct ufs_vreg_info vreg_info;
struct list_head clk_list_head;
+ bool use_pm_opp;

/* Number of requests aborts */
int req_abort_count;
--
2.25.1

2023-10-12 17:24:40

by Manivannan Sadhasivam

[permalink] [raw]
Subject: [PATCH v7 4/5] arm64: dts: qcom: sdm845: Add OPP table support to UFSHC

From: Krzysztof Kozlowski <[email protected]>

UFS host controller, when scaling gears, should choose appropriate
performance state of RPMh power domain controller along with clock
frequency. So let's add the OPP table support to specify both clock
frequency and RPMh performance states replacing the old "freq-table-hz"
property.

Reviewed-by: Dmitry Baryshkov <[email protected]>
Signed-off-by: Krzysztof Kozlowski <[email protected]>
[mani: Splitted pd change and used rpmhpd_opp_low_svs]
Signed-off-by: Manivannan Sadhasivam <[email protected]>
---
arch/arm64/boot/dts/qcom/sdm845.dtsi | 42 +++++++++++++++++++++-------
1 file changed, 32 insertions(+), 10 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index 055ca80c0075..2ea6eb44953e 100644
--- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
@@ -2605,22 +2605,44 @@ ufs_mem_hc: ufshc@1d84000 {
<&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
<&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>,
<&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
- freq-table-hz =
- <50000000 200000000>,
- <0 0>,
- <0 0>,
- <37500000 150000000>,
- <0 0>,
- <0 0>,
- <0 0>,
- <0 0>,
- <75000000 300000000>;
+
+ operating-points-v2 = <&ufs_opp_table>;

interconnects = <&aggre1_noc MASTER_UFS_MEM 0 &mem_noc SLAVE_EBI1 0>,
<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_UFS_MEM_CFG 0>;
interconnect-names = "ufs-ddr", "cpu-ufs";

status = "disabled";
+
+ ufs_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-50000000 {
+ opp-hz = /bits/ 64 <50000000>,
+ /bits/ 64 <0>,
+ /bits/ 64 <0>,
+ /bits/ 64 <37500000>,
+ /bits/ 64 <0>,
+ /bits/ 64 <0>,
+ /bits/ 64 <0>,
+ /bits/ 64 <0>,
+ /bits/ 64 <75000000>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ };
+
+ opp-200000000 {
+ opp-hz = /bits/ 64 <200000000>,
+ /bits/ 64 <0>,
+ /bits/ 64 <0>,
+ /bits/ 64 <150000000>,
+ /bits/ 64 <0>,
+ /bits/ 64 <0>,
+ /bits/ 64 <0>,
+ /bits/ 64 <0>,
+ /bits/ 64 <300000000>;
+ required-opps = <&rpmhpd_opp_nom>;
+ };
+ };
};

ufs_mem_phy: phy@1d87000 {
--
2.25.1

2023-10-12 17:25:09

by Manivannan Sadhasivam

[permalink] [raw]
Subject: [PATCH v7 3/5] scsi: ufs: host: Add support for parsing OPP

OPP framework can be used to scale the clocks along with other entities
such as regulators, performance state etc... So let's add support for
parsing OPP from devicetree. OPP support in devicetree is added through
the "operating-points-v2" property which accepts the OPP table defining
clock frequency, regulator voltage, power domain performance state etc...

Since the UFS controller requires multiple clocks to be controlled for
proper working, devm_pm_opp_set_config() has been used which supports
scaling multiple clocks through custom ufshcd_opp_config_clks() callback.

It should be noted that the OPP support is not compatible with the old
"freq-table-hz" property. So only one can be used at a time even though
the UFS core supports both.

Co-developed-by: Krzysztof Kozlowski <[email protected]>
Signed-off-by: Krzysztof Kozlowski <[email protected]>
Signed-off-by: Manivannan Sadhasivam <[email protected]>
---
drivers/ufs/core/ufshcd.c | 36 +++++++++++++++
drivers/ufs/host/ufshcd-pltfrm.c | 78 ++++++++++++++++++++++++++++++++
include/ufs/ufshcd.h | 3 ++
3 files changed, 117 insertions(+)

diff --git a/drivers/ufs/core/ufshcd.c b/drivers/ufs/core/ufshcd.c
index 3f52e05002e4..a729be3e1f1c 100644
--- a/drivers/ufs/core/ufshcd.c
+++ b/drivers/ufs/core/ufshcd.c
@@ -1064,6 +1064,42 @@ static int ufshcd_set_clk_freq(struct ufs_hba *hba, bool scale_up)
return ret;
}

+int ufshcd_opp_config_clks(struct device *dev, struct opp_table *opp_table,
+ struct dev_pm_opp *opp, void *data,
+ bool scaling_down)
+{
+ struct ufs_hba *hba = dev_get_drvdata(dev);
+ struct list_head *head = &hba->clk_list_head;
+ struct ufs_clk_info *clki;
+ unsigned long freq;
+ u8 idx = 0;
+ int ret;
+
+ list_for_each_entry(clki, head, list) {
+ if (!IS_ERR_OR_NULL(clki->clk)) {
+ freq = dev_pm_opp_get_freq_indexed(opp, idx++);
+
+ /* Do not set rate for clocks having frequency as 0 */
+ if (!freq)
+ continue;
+
+ ret = clk_set_rate(clki->clk, freq);
+ if (ret) {
+ dev_err(dev, "%s: %s clk set rate(%ldHz) failed, %d\n",
+ __func__, clki->name, freq, ret);
+ return ret;
+ }
+
+ trace_ufshcd_clk_scaling(dev_name(dev),
+ (scaling_down ? "scaled down" : "scaled up"),
+ clki->name, hba->clk_scaling.target_freq, freq);
+ }
+ }
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(ufshcd_opp_config_clks);
+
static int ufshcd_opp_set_rate(struct ufs_hba *hba, unsigned long freq)
{
struct dev_pm_opp *opp;
diff --git a/drivers/ufs/host/ufshcd-pltfrm.c b/drivers/ufs/host/ufshcd-pltfrm.c
index 61cf8b957da4..da2558e274b4 100644
--- a/drivers/ufs/host/ufshcd-pltfrm.c
+++ b/drivers/ufs/host/ufshcd-pltfrm.c
@@ -10,6 +10,7 @@

#include <linux/module.h>
#include <linux/platform_device.h>
+#include <linux/pm_opp.h>
#include <linux/pm_runtime.h>
#include <linux/of.h>

@@ -212,6 +213,77 @@ static void ufshcd_init_lanes_per_dir(struct ufs_hba *hba)
}
}

+static int ufshcd_parse_operating_points(struct ufs_hba *hba)
+{
+ struct device *dev = hba->dev;
+ struct device_node *np = dev->of_node;
+ struct dev_pm_opp_config config = {};
+ struct ufs_clk_info *clki;
+ const char **clk_names;
+ int cnt, i, ret;
+
+ if (!of_find_property(np, "operating-points-v2", NULL))
+ return 0;
+
+ if (of_find_property(np, "freq-table-hz", NULL)) {
+ dev_err(dev, "%s: operating-points and freq-table-hz are incompatible\n",
+ __func__);
+ return -EINVAL;
+ }
+
+ cnt = of_property_count_strings(np, "clock-names");
+ if (cnt <= 0) {
+ dev_err(dev, "%s: Missing clock-names\n", __func__);
+ return -ENODEV;
+ }
+
+ /* OPP expects clk_names to be NULL terminated */
+ clk_names = devm_kcalloc(dev, cnt + 1, sizeof(*clk_names), GFP_KERNEL);
+ if (!clk_names)
+ return -ENOMEM;
+
+ /*
+ * We still need to get reference to all clocks as the UFS core uses
+ * them separately.
+ */
+ for (i = 0; i < cnt; i++) {
+ ret = of_property_read_string_index(np, "clock-names", i,
+ &clk_names[i]);
+ if (ret)
+ return ret;
+
+ clki = devm_kzalloc(dev, sizeof(*clki), GFP_KERNEL);
+ if (!clki)
+ return -ENOMEM;
+
+ clki->name = devm_kstrdup(dev, clk_names[i], GFP_KERNEL);
+ if (!clki->name)
+ return -ENOMEM;
+
+ if (!strcmp(clk_names[i], "ref_clk"))
+ clki->keep_link_active = true;
+
+ list_add_tail(&clki->list, &hba->clk_list_head);
+ }
+
+ config.clk_names = clk_names,
+ config.config_clks = ufshcd_opp_config_clks;
+
+ ret = devm_pm_opp_set_config(dev, &config);
+ if (ret)
+ return ret;
+
+ ret = devm_pm_opp_of_add_table(dev);
+ if (ret) {
+ dev_err(dev, "Failed to add OPP table: %d\n", ret);
+ return ret;
+ }
+
+ hba->use_pm_opp = true;
+
+ return 0;
+}
+
/**
* ufshcd_get_pwr_dev_param - get finally agreed attributes for
* power mode change
@@ -378,6 +450,12 @@ int ufshcd_pltfrm_init(struct platform_device *pdev,

ufshcd_init_lanes_per_dir(hba);

+ err = ufshcd_parse_operating_points(hba);
+ if (err) {
+ dev_err(dev, "%s: OPP parse failed %d\n", __func__, err);
+ goto dealloc_host;
+ }
+
err = ufshcd_init(hba, mmio_base, irq);
if (err) {
dev_err_probe(dev, err, "Initialization failed with error %d\n",
diff --git a/include/ufs/ufshcd.h b/include/ufs/ufshcd.h
index fc0d6d37319a..7f0b2c5599cd 100644
--- a/include/ufs/ufshcd.h
+++ b/include/ufs/ufshcd.h
@@ -1254,6 +1254,9 @@ void ufshcd_mcq_make_queues_operational(struct ufs_hba *hba);
void ufshcd_mcq_enable_esi(struct ufs_hba *hba);
void ufshcd_mcq_config_esi(struct ufs_hba *hba, struct msi_msg *msg);

+int ufshcd_opp_config_clks(struct device *dev, struct opp_table *opp_table,
+ struct dev_pm_opp *opp, void *data,
+ bool scaling_down);
/**
* ufshcd_set_variant - set variant specific data to the hba
* @hba: per adapter instance
--
2.25.1

2023-10-12 17:25:13

by Manivannan Sadhasivam

[permalink] [raw]
Subject: [PATCH v7 5/5] arm64: dts: qcom: sm8250: Add OPP table support to UFSHC

UFS host controller, when scaling gears, should choose appropriate
performance state of RPMh power domain controller along with clock
frequency. So let's add the OPP table support to specify both clock
frequency and RPMh performance states replacing the old "freq-table-hz"
property.

Reviewed-by: Dmitry Baryshkov <[email protected]>
Signed-off-by: Manivannan Sadhasivam <[email protected]>
---
arch/arm64/boot/dts/qcom/sm8250.dtsi | 39 +++++++++++++++++++++-------
1 file changed, 30 insertions(+), 9 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi
index a4e58ad731c3..33abd84aae53 100644
--- a/arch/arm64/boot/dts/qcom/sm8250.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi
@@ -2198,21 +2198,42 @@ ufs_mem_hc: ufshc@1d84000 {
<&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
<&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
<&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
- freq-table-hz =
- <37500000 300000000>,
- <0 0>,
- <0 0>,
- <37500000 300000000>,
- <0 0>,
- <0 0>,
- <0 0>,
- <0 0>;
+
+ operating-points-v2 = <&ufs_opp_table>;

interconnects = <&aggre1_noc MASTER_UFS_MEM 0 &mc_virt SLAVE_EBI_CH0 0>,
<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_UFS_MEM_CFG 0>;
interconnect-names = "ufs-ddr", "cpu-ufs";

status = "disabled";
+
+ ufs_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-37500000 {
+ opp-hz = /bits/ 64 <37500000>,
+ /bits/ 64 <0>,
+ /bits/ 64 <0>,
+ /bits/ 64 <37500000>,
+ /bits/ 64 <0>,
+ /bits/ 64 <0>,
+ /bits/ 64 <0>,
+ /bits/ 64 <0>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ };
+
+ opp-300000000 {
+ opp-hz = /bits/ 64 <300000000>,
+ /bits/ 64 <0>,
+ /bits/ 64 <0>,
+ /bits/ 64 <300000000>,
+ /bits/ 64 <0>,
+ /bits/ 64 <0>,
+ /bits/ 64 <0>,
+ /bits/ 64 <0>;
+ required-opps = <&rpmhpd_opp_nom>;
+ };
+ };
};

ufs_mem_phy: phy@1d87000 {
--
2.25.1

2023-10-16 04:01:20

by Manivannan Sadhasivam

[permalink] [raw]
Subject: Re: [PATCH v7 0/5] UFS: Add OPP support

On Thu, Oct 12, 2023 at 10:51:24PM +0530, Manivannan Sadhasivam wrote:
> Hi,
>
> This series adds OPP (Operating Points) support to UFSHCD driver.
>
> Motivation behind adding OPP support is to scale both clocks as well as
> regulators/performance state dynamically. Currently, UFSHCD just scales
> clock frequency during runtime with the help of "freq-table-hz" property
> defined in devicetree. With the addition of OPP tables in devicetree (as
> done for Qcom SDM845 and SM8250 SoCs in this series) UFSHCD can now scale
> both clocks and performance state of power domain which helps in power
> saving.
>
> For the addition of OPP support to UFSHCD, there are changes required to
> the OPP framework and devfreq drivers. The OPP framework changes are already
> merged and the devfreq change is added in this series.
>
> Credits
> =======
>
> This series is a continuation of previous work by Krzysztof Kozlowski [1].
>
> Testing
> =======
>
> This series is tested on 96Boards RB3 (SDM845 SoC) and RB5 (SM8250 SoC)
> development boards.
>
> Merging Strategy
> ================
>
> Since the devfreq patch got an Ack from the maintainer, either it can be merged
> to scsi tree with rest of the patches or merged separately through devfreq tree.
>

Martin, can you please merge the ufs patches (drivers,bindings) for v6.7? Note
that the devfreq patch already got merged and the above text is outdated (my
bad).

- Mani

> Thanks,
> Mani
>
> [1] https://lore.kernel.org/all/[email protected]/
>
> Changes in v7:
>
> * Added missing EXPORT_SYMBOL_GPL() for ufshcd_opp_config_clks() API as reported
> by Alessandro Carminati
>
> Changes in v6:
>
> * Collected tags from Dmitry
> * Fixed bindings issues reported by Krzysztof
>
> Changes in v5:
>
> * Dropped the devfreq patch since it got applied
> * Fixed the bindings issue reported by DT bot
> * Rebased on top of mkp/scsi/for-next
>
> Changes in v4:
>
> * Rebased on top of v6.6-rc3
>
> Changes in v3:
>
> * Rebased on top of linux-next/master tag: next-20230731
> * Dropped the already applied patches (dts, opp binding and framework)
> * Moved the interconnect patches to a separate series:
> https://lore.kernel.org/linux-scsi/[email protected]/
> * Moved ufshcd_opp_config_clks() API to ufshcd.c to fix the build failure
> reported by Kbuild bot: https://lore.kernel.org/all/[email protected]/
> * Collected Acks
> * v2: https://lore.kernel.org/all/[email protected]/
>
> Changes in v2:
>
> * Added more description to the bindings patch 2/15
> * Fixed dev_pm_opp_put() usage in patch 10/15
> * Added a new patch for adding enums for UFS lanes 14/15
> * Changed the icc variables to mem_bw and cfg_bw and used
> the enums for gears and lanes in bw_table
> * Collected review tags
> * Added SCSI list and folks
> * Removed duplicate patches
>
> Krzysztof Kozlowski (2):
> dt-bindings: ufs: common: add OPP table
> arm64: dts: qcom: sdm845: Add OPP table support to UFSHC
>
> Manivannan Sadhasivam (3):
> scsi: ufs: core: Add OPP support for scaling clocks and regulators
> scsi: ufs: host: Add support for parsing OPP
> arm64: dts: qcom: sm8250: Add OPP table support to UFSHC
>
> .../devicetree/bindings/ufs/ufs-common.yaml | 35 +++-
> arch/arm64/boot/dts/qcom/sdm845.dtsi | 42 +++-
> arch/arm64/boot/dts/qcom/sm8250.dtsi | 39 +++-
> drivers/ufs/core/ufshcd.c | 180 ++++++++++++++----
> drivers/ufs/host/ufshcd-pltfrm.c | 78 ++++++++
> include/ufs/ufshcd.h | 7 +
> 6 files changed, 326 insertions(+), 55 deletions(-)
>
> --
> 2.25.1
>

--
மணிவண்ணன் சதாசிவம்

2023-10-17 01:01:02

by Martin K. Petersen

[permalink] [raw]
Subject: Re: [PATCH v7 0/5] UFS: Add OPP support


Manivannan,

> Martin, can you please merge the ufs patches (drivers,bindings) for
> v6.7? Note that the devfreq patch already got merged and the above
> text is outdated (my bad).

Applied to 6.7/scsi-staging, thanks!

--
Martin K. Petersen Oracle Linux Engineering

2023-10-25 02:20:41

by Martin K. Petersen

[permalink] [raw]
Subject: Re: (subset) [PATCH v7 0/5] UFS: Add OPP support

On Thu, 12 Oct 2023 22:51:24 +0530, Manivannan Sadhasivam wrote:

> This series adds OPP (Operating Points) support to UFSHCD driver.
>
> Motivation behind adding OPP support is to scale both clocks as well as
> regulators/performance state dynamically. Currently, UFSHCD just scales
> clock frequency during runtime with the help of "freq-table-hz" property
> defined in devicetree. With the addition of OPP tables in devicetree (as
> done for Qcom SDM845 and SM8250 SoCs in this series) UFSHCD can now scale
> both clocks and performance state of power domain which helps in power
> saving.
>
> [...]

Applied to 6.7/scsi-queue, thanks!

[1/5] dt-bindings: ufs: common: add OPP table
https://git.kernel.org/mkp/scsi/c/e820de1d115f
[2/5] scsi: ufs: core: Add OPP support for scaling clocks and regulators
https://git.kernel.org/mkp/scsi/c/930bd77ebe3d
[3/5] scsi: ufs: host: Add support for parsing OPP
https://git.kernel.org/mkp/scsi/c/72208ebe181e

--
Martin K. Petersen Oracle Linux Engineering

2023-12-03 04:53:34

by Bjorn Andersson

[permalink] [raw]
Subject: Re: (subset) [PATCH v7 0/5] UFS: Add OPP support


On Thu, 12 Oct 2023 22:51:24 +0530, Manivannan Sadhasivam wrote:
> This series adds OPP (Operating Points) support to UFSHCD driver.
>
> Motivation behind adding OPP support is to scale both clocks as well as
> regulators/performance state dynamically. Currently, UFSHCD just scales
> clock frequency during runtime with the help of "freq-table-hz" property
> defined in devicetree. With the addition of OPP tables in devicetree (as
> done for Qcom SDM845 and SM8250 SoCs in this series) UFSHCD can now scale
> both clocks and performance state of power domain which helps in power
> saving.
>
> [...]

Applied, thanks!

[4/5] arm64: dts: qcom: sdm845: Add OPP table support to UFSHC
commit: ec987b5efd59fdea4178d824d8ec4bbdf3019bdf
[5/5] arm64: dts: qcom: sm8250: Add OPP table support to UFSHC
commit: 725be1d6318e4ea7e3947fd4242a14cf589cfebf

Best regards,
--
Bjorn Andersson <[email protected]>

2023-12-04 12:03:39

by Manivannan Sadhasivam

[permalink] [raw]
Subject: Re: (subset) [PATCH v7 0/5] UFS: Add OPP support

On Sat, Dec 02, 2023 at 08:54:46PM -0800, Bjorn Andersson wrote:
>
> On Thu, 12 Oct 2023 22:51:24 +0530, Manivannan Sadhasivam wrote:
> > This series adds OPP (Operating Points) support to UFSHCD driver.
> >
> > Motivation behind adding OPP support is to scale both clocks as well as
> > regulators/performance state dynamically. Currently, UFSHCD just scales
> > clock frequency during runtime with the help of "freq-table-hz" property
> > defined in devicetree. With the addition of OPP tables in devicetree (as
> > done for Qcom SDM845 and SM8250 SoCs in this series) UFSHCD can now scale
> > both clocks and performance state of power domain which helps in power
> > saving.
> >
> > [...]
>
> Applied, thanks!
>
> [4/5] arm64: dts: qcom: sdm845: Add OPP table support to UFSHC
> commit: ec987b5efd59fdea4178d824d8ec4bbdf3019bdf
> [5/5] arm64: dts: qcom: sm8250: Add OPP table support to UFSHC
> commit: 725be1d6318e4ea7e3947fd4242a14cf589cfebf
>

Bjorn, could you please drop these two patches? I found the OPP regression in
the ufs-qcom driver due to some patches that got merged last cycle. Nitin is
working on a fix for that. So I'd like to defer merging of these dts patches to
v6.9.

I can resend them after v6.8-rc1.

- Mani

> Best regards,
> --
> Bjorn Andersson <[email protected]>

--
மணிவண்ணன் சதாசிவம்

2023-12-05 20:56:55

by Marek Szyprowski

[permalink] [raw]
Subject: Re: [PATCH v7 5/5] arm64: dts: qcom: sm8250: Add OPP table support to UFSHC

On 12.10.2023 19:21, Manivannan Sadhasivam wrote:
> UFS host controller, when scaling gears, should choose appropriate
> performance state of RPMh power domain controller along with clock
> frequency. So let's add the OPP table support to specify both clock
> frequency and RPMh performance states replacing the old "freq-table-hz"
> property.
>
> Reviewed-by: Dmitry Baryshkov <[email protected]>
> Signed-off-by: Manivannan Sadhasivam <[email protected]>
> ---


This patch landed in today's linux-next as commit 725be1d6318e ("arm64:
dts: qcom: sm8250: Add OPP table support to UFSHC"). Unfortunately it
breaks booting of my RB5 board with the following messages:

 ufshcd-qcom 1d84000.ufshc: Adding to iommu group 5
 ufshcd-qcom 1d84000.ufshc: freq-table-hz property not specified
 ufshcd-qcom 1d84000.ufshc: ufshcd_populate_vreg: Unable to find
vdd-hba-supply regulator, assuming enabled
 ufshcd-qcom 1d84000.ufshc: freq-table-hz property not specified
 ufshcd-qcom 1d84000.ufshc: ufshcd_populate_vreg: Unable to find
vdd-hba-supply regulator, assuming enabled
 scsi host0: ufshcd
 ufshcd-qcom 1d84000.ufshc: UNIPRO clk freq 0 MHz not supported
 ufshcd-qcom 1d84000.ufshc: cfg core clk ctrl failed
 clk: Disabling unused clocks
 ALSA device list:
   No soundcards found.
 Waiting 2 sec before mounting root device...
 ufshcd-qcom 1d84000.ufshc: uic cmd 0x16 with arg3 0x0 completion timeout
 ufshcd-qcom 1d84000.ufshc: Controller enable failed
 ufshcd-qcom 1d84000.ufshc: Controller enable failed
 ufshcd-qcom 1d84000.ufshc: Controller enable failed
 ufshcd-qcom 1d84000.ufshc: Controller enable failed
 ufshcd-qcom 1d84000.ufshc: link startup failed -110
 ufshcd-qcom 1d84000.ufshc: UFS Host state=0
 ufshcd-qcom 1d84000.ufshc: outstanding reqs=0x0 tasks=0x0
 ufshcd-qcom 1d84000.ufshc: saved_err=0x0, saved_uic_err=0x0
 ufshcd-qcom 1d84000.ufshc: Device power mode=1, UIC link state=0
 ufshcd-qcom 1d84000.ufshc: PM in progress=0, sys. suspended=0
 ufshcd-qcom 1d84000.ufshc: Auto BKOPS=0, Host self-block=0
 ufshcd-qcom 1d84000.ufshc: Clk gate=1
 ufshcd-qcom 1d84000.ufshc: last_hibern8_exit_tstamp at 0 us,
hibern8_exit_cnt=0
 ufshcd-qcom 1d84000.ufshc: last intr at 2889168 us, last intr status=0x400
 ufshcd-qcom 1d84000.ufshc: error handling flags=0x0, req. abort count=0
 ufshcd-qcom 1d84000.ufshc: hba->ufs_version=0x300, Host
capabilities=0x1587031f, caps=0x12cf
 ufshcd-qcom 1d84000.ufshc: quirks=0x80000, dev. quirks=0x0
 host_regs: 00000000: 1587031f 00000000 00000300 00000000
 host_regs: 00000010: 01000000 00010217 00000000 00000000
 host_regs: 00000020: 00000000 00000000 00000000 00000000
 host_regs: 00000030: 00000008 00000000 00000000 00000000
 host_regs: 00000040: 00000000 00000000 00000000 00000000
 host_regs: 00000050: 00000000 00000000 00000000 00000000
 host_regs: 00000060: 00000000 00000000 00000000 00000000
 host_regs: 00000070: 00000000 00000000 00000000 00000000
 host_regs: 00000080: 00000000 00000000 00000000 00000000
 host_regs: 00000090: 00000000 00000001 00000000 00000000
 ufshcd-qcom 1d84000.ufshc: No record of pa_err
 ufshcd-qcom 1d84000.ufshc: No record of dl_err
 ufshcd-qcom 1d84000.ufshc: No record of nl_err
 ufshcd-qcom 1d84000.ufshc: No record of tl_err
 ufshcd-qcom 1d84000.ufshc: No record of dme_err
 ufshcd-qcom 1d84000.ufshc: No record of auto_hibern8_err
 ufshcd-qcom 1d84000.ufshc: No record of fatal_err
 ufshcd-qcom 1d84000.ufshc: link_startup_fail[0] = 0xffffff92 at 3663462 us
 ufshcd-qcom 1d84000.ufshc: link_startup_fail: total cnt=1
 ufshcd-qcom 1d84000.ufshc: No record of resume_fail
 ufshcd-qcom 1d84000.ufshc: No record of suspend_fail
 ufshcd-qcom 1d84000.ufshc: No record of wlun resume_fail
 ufshcd-qcom 1d84000.ufshc: No record of wlun suspend_fail
 ufshcd-qcom 1d84000.ufshc: No record of dev_reset
 ufshcd-qcom 1d84000.ufshc: No record of host_reset
 ufshcd-qcom 1d84000.ufshc: No record of task_abort
 HCI Vendor Specific Registers 00000000: 0000012c 00000000 00000000
00000000
 HCI Vendor Specific Registers 00000010: 00000042 00000000 00000001
1c00052c
 HCI Vendor Specific Registers 00000020: 3f011300 40020000 00000000
00000000
 HCI Vendor Specific Registers 00000030: 00000000 00000000 00000000
00000000
 UFS_UFS_DBG_RD_REG_OCSC 00000000: 00000000 00000000 00000000 00000000
 UFS_UFS_DBG_RD_REG_OCSC 00000010: 00000000 00000000 00000000 00000000
 UFS_UFS_DBG_RD_REG_OCSC 00000020: 00000000 00000000 00000000 00000000
 UFS_UFS_DBG_RD_REG_OCSC 00000030: 00000000 00000000 00000000 00000000
 UFS_UFS_DBG_RD_REG_OCSC 00000040: 00000000 00000000 00000000 00000000
 UFS_UFS_DBG_RD_REG_OCSC 00000050: 00000000 00000000 00000000 00000000
 UFS_UFS_DBG_RD_REG_OCSC 00000060: 00000000 00000000 00000000 00000000
 UFS_UFS_DBG_RD_REG_OCSC 00000070: 00000000 00000000 00000000 00000000
 UFS_UFS_DBG_RD_REG_OCSC 00000080: 00000000 00000000 00000000 00000000
 UFS_UFS_DBG_RD_REG_OCSC 00000090: 00000000 00000000 00000000 00000000
 UFS_UFS_DBG_RD_REG_OCSC 000000a0: 00000000 00000000 00000000 00000000
 UFS_UFS_DBG_RD_EDTL_RAM 00000000: 00000000 7147f7fd 47857989 b7556f16
 UFS_UFS_DBG_RD_EDTL_RAM 00000010: ad69b114 7cd5fd55 41d57796 0e55e717
 UFS_UFS_DBG_RD_EDTL_RAM 00000020: 04558745 efc573b5 4f35f49b b2697d16
 UFS_UFS_DBG_RD_EDTL_RAM 00000030: 5c7563d5 7755f4d6 cf65dd90 6591d535
 UFS_UFS_DBG_RD_EDTL_RAM 00000040: 4151f597 ffaf75a9 57442485 f7654511
 UFS_UFS_DBG_RD_EDTL_RAM 00000050: fc57e046 ff57f5b5 c7c53417 adb56f55
 UFS_UFS_DBG_RD_EDTL_RAM 00000060: 9b753f4c 5155a115 245525f1 77755d51
 UFS_UFS_DBG_RD_EDTL_RAM 00000070: 5791ffdf 77555756 7cd5b941 431ce192
 UFS_UFS_DBG_RD_DESC_RAM 00000000: 7dfffedf 001fbffb ff7fffff 003ffffd
 UFS_UFS_DBG_RD_DESC_RAM 00000010: 7f3dfff5 003fffff 7ffdfff3 0017fff7
 UFS_UFS_DBG_RD_DESC_RAM 00000020: 3fdd595f 003ff5b7 ffffdfdf 003f77f7
 UFS_UFS_DBG_RD_DESC_RAM 00000030: fffff7d7 003f75f7 7fffffff 0037ffff
 UFS_UFS_DBG_RD_DESC_RAM 00000040: fdff7f7f 003f57df fdfeffbf 003ffff7
 UFS_UFS_DBG_RD_DESC_RAM 00000050: 7d7d7fff 00379d7f 7ffd7fff 001f3fff
 UFS_UFS_DBG_RD_DESC_RAM 00000060: 7f7fdeff 003fffd5 f7f7fffd 003fffff
 UFS_UFS_DBG_RD_DESC_RAM 00000070: 777ffd7d 003ffd75 ff7ffffd 003f7ffd
 UFS_UFS_DBG_RD_DESC_RAM 00000080: ff15fddf 003edfd7 df5ffff7 003fffdf
 UFS_UFS_DBG_RD_DESC_RAM 00000090: ffe57f5f 003fbff7 ddd7ff75 003f7fff
 UFS_UFS_DBG_RD_DESC_RAM 000000a0: fd4ffffd 003dddff eefffff7 003fbfff
 UFS_UFS_DBG_RD_DESC_RAM 000000b0: 67fffffd 001ff7fd bdd75f7f 0031bfff
 UFS_UFS_DBG_RD_DESC_RAM 000000c0: ffdddf75 003fff5d 7f5fffdd 002f7fdf
 UFS_UFS_DBG_RD_DESC_RAM 000000d0: ff7d5ffd 0037fdff df675fd5 001ffbdf
 UFS_UFS_DBG_RD_DESC_RAM 000000e0: b5ff7dff 00337ffc ff7ff7fb 003ffff7
 UFS_UFS_DBG_RD_DESC_RAM 000000f0: 5ffdffdd 001ddfff 75ffddff 003fffff
 UFS_UFS_DBG_RD_DESC_RAM 00000100: ff5f5fdf 003d37bf ff77dfff 0017edb7
 UFS_UFS_DBG_RD_DESC_RAM 00000110: ff7ff7ff 003ffd7f ff5f7fdd 003f3fd7
 UFS_UFS_DBG_RD_DESC_RAM 00000120: 7fffffdf 003ff5d9 55ffffdf 003f79d5
 UFS_UFS_DBG_RD_DESC_RAM 00000130: d5ffe7f5 002767fe ffdd75df 003d7fdf
 UFS_UFS_DBG_RD_DESC_RAM 00000140: 7fff77ff 003dff5f 7d7ff7ff 002f7fff
 UFS_UFS_DBG_RD_DESC_RAM 00000150: fdff7ddf 003fe7dd 5df77ddd 0037f7ff
 UFS_UFS_DBG_RD_DESC_RAM 00000160: f7f16977 003f9fdf 5775ff77 00357ff5
 UFS_UFS_DBG_RD_DESC_RAM 00000170: 7ffdfffb 003dff5f 7f7f77f7 003fffff
 UFS_UFS_DBG_RD_DESC_RAM 00000180: 57dff7df 003dffff fffdd7ff 001efffd
 UFS_UFS_DBG_RD_DESC_RAM 00000190: 7dffffed 003f7fce 77d9f7ff 001fdddd
 UFS_UFS_DBG_RD_DESC_RAM 000001a0: ddffdffd 001fd57d 7f7ff777 003f78dd
 UFS_UFS_DBG_RD_DESC_RAM 000001b0: d5eff77f 0037dfdf ed7d77ff 003ffffd
 UFS_UFS_DBG_RD_DESC_RAM 000001c0: cf7fdfff 001f5f7e ffffffff 003f57df
 UFS_UFS_DBG_RD_DESC_RAM 000001d0: fdfffffd 003f7dff 556ffddf 003fdd7f
 UFS_UFS_DBG_RD_DESC_RAM 000001e0: fdff71df 003e7fff ff3f7fd7 0037f77b
 UFS_UFS_DBG_RD_DESC_RAM 000001f0: 7f7f7677 00355fdf 7feffdff 0037ffff
 UFS_UFS_DBG_RD_PRDT_RAM 00000000: d1700001 0000192c 3d9edf71 00075d51
 UFS_UFS_DBG_RD_PRDT_RAM 00000010: 4561073f 0000415d ddde6dd9 000ff55f
 UFS_UFS_DBG_RD_PRDT_RAM 00000020: adb7185f 000df971 579caffd 000de54d
 UFS_UFS_DBG_RD_PRDT_RAM 00000030: 45e55747 00057559 7f5e5dbd 000377df
 UFS_UFS_DBG_RD_PRDT_RAM 00000040: dd175467 0007dc9c 4e775d77 0007555f
 UFS_UFS_DBG_RD_PRDT_RAM 00000050: 1f15dd77 000d195d f1c9e535 0007b75f
 UFS_UFS_DBG_RD_PRDT_RAM 00000060: 15bd75f3 0007675f dfd59d77 00057b5c
 UFS_UFS_DBG_RD_PRDT_RAM 00000070: d4f09dee 00017d39 52857d56 000c6ddd
 UFS_UFS_DBG_RD_PRDT_RAM 00000080: c333fcd6 000545df 1d57f51d 000577e9
 UFS_UFS_DBG_RD_PRDT_RAM 00000090: 9f83d45d 00055d18 d4e7d7ee 000713df
 UFS_UFS_DBG_RD_PRDT_RAM 000000a0: fdfe39d7 000754df d54f5d77 000746f1
 UFS_UFS_DBG_RD_PRDT_RAM 000000b0: 5a40c5f5 000c45d4 17471fe3 000e9d1d
 UFS_UFS_DBG_RD_PRDT_RAM 000000c0: 1747dd5f 00074577 d540d75d 00044d67
 UFS_UFS_DBG_RD_PRDT_RAM 000000d0: de3545d3 000c4757 5f845115 00063795
 UFS_UFS_DBG_RD_PRDT_RAM 000000e0: d15d776c 000c7fd5 1f5f5d75 00067d75
 UFS_UFS_DBG_RD_PRDT_RAM 000000f0: d71d4c7d 0007bd13 7557d77d 000355df
 UFS_DBG_RD_REG_UAWM 00000000: 00000000 0fe00000 00000004 f4000102
 UFS_DBG_RD_REG_UARM 00000000: 00000000 00000000 00000001 00000001
 UFS_DBG_RD_REG_TXUC 00000000: 00000000 00000000 00000000 00000000
 UFS_DBG_RD_REG_TXUC 00000010: 00000000 00000000 00000000 00000000
 UFS_DBG_RD_REG_TXUC 00000020: 00000000 00000000 00000000 00000000
 UFS_DBG_RD_REG_TXUC 00000030: 00000000 00000000 00000000 00000000
 UFS_DBG_RD_REG_TXUC 00000040: 00000000 00000000 00000000 00000000
 UFS_DBG_RD_REG_TXUC 00000050: 00000000 00000000 00000000 00000000
 UFS_DBG_RD_REG_TXUC 00000060: 00000000 00000000 00000000 00000000
 UFS_DBG_RD_REG_TXUC 00000070: 00000000 00000000 00000000 00000000
 UFS_DBG_RD_REG_TXUC 00000080: 00000000 00000000 00000000 00000000
 UFS_DBG_RD_REG_TXUC 00000090: 00000000 00000000 00000000 00000000
 UFS_DBG_RD_REG_TXUC 000000a0: 00000000 00000000 00000000 00000000
 UFS_DBG_RD_REG_TXUC 000000b0: 00000001 00000000 00000000 00000004
 UFS_DBG_RD_REG_RXUC 00000000: 00000000 00000000 00000000 00000004
 UFS_DBG_RD_REG_RXUC 00000010: 00000000 00000000 00000000 00000000
 UFS_DBG_RD_REG_RXUC 00000020: 00000000 00000000 00000000 00000000
 UFS_DBG_RD_REG_RXUC 00000030: 00000000 00000000 00000000 00000000
 UFS_DBG_RD_REG_RXUC 00000040: 00000000 00000000 00000000 00000000
 UFS_DBG_RD_REG_RXUC 00000050: 00000000 00000000 00000000 00000001
 UFS_DBG_RD_REG_RXUC 00000060: 00000000 00000000 00000004
 UFS_DBG_RD_REG_DFC 00000000: 00000000 00000000 00000000 00000000
 UFS_DBG_RD_REG_DFC 00000010: 00000000 00000000 00000000 00000000
 UFS_DBG_RD_REG_DFC 00000020: 00000000 00000000 00000000 00000000
 UFS_DBG_RD_REG_DFC 00000030: 00000000 00000000 00000000 00000000
 UFS_DBG_RD_REG_DFC 00000040: ffffffff 00000000 00000000
 UFS_DBG_RD_REG_TRLUT 00000000: 00000000 00000000 00000000 00000000
 UFS_DBG_RD_REG_TRLUT 00000010: 00000000 00000000 00000000 00000000
 UFS_DBG_RD_REG_TRLUT 00000020: 00000000 00000000 00000000 00000000
 UFS_DBG_RD_REG_TRLUT 00000030: 00000000 00000000 00000000 00000000
 UFS_DBG_RD_REG_TRLUT 00000040: 00000000 00000000 00000000 00000000
 UFS_DBG_RD_REG_TRLUT 00000050: 00000000 00000000 00000000 00000000
 UFS_DBG_RD_REG_TRLUT 00000060: 00000000 00000000 00000000 00000000
 UFS_DBG_RD_REG_TRLUT 00000070: 00000000 00000000 00000000 00000000
 UFS_DBG_RD_REG_TRLUT 00000080: 00000000 00000000
 UFS_DBG_RD_REG_TMRLUT 00000000: 00000000 00000000 00000000 00000000
 UFS_DBG_RD_REG_TMRLUT 00000010: 00000000 00000000 00000000 00000000
 UFS_DBG_RD_REG_TMRLUT 00000020: 00000000
 ------------[ cut here ]------------
 gcc_ufs_phy_axi_clk status stuck at 'off'
 WARNING: CPU: 3 PID: 103 at drivers/clk/qcom/clk-branch.c:86
clk_branch_wait+0x144/0x15c
 Modules linked in:
 CPU: 3 PID: 103 Comm: kworker/u17:0 Not tainted
6.7.0-rc4-next-20231205 #14278
 Hardware name: Qualcomm Technologies, Inc. Robotics RB5 (DT)
 Workqueue: ufs_clk_gating_0 ufshcd_ungate_work
 pstate: 604000c5 (nZCv daIF +PAN -UAO -TCO -DIT -SSBS BTYPE=--)
 pc : clk_branch_wait+0x144/0x15c
 lr : clk_branch_wait+0x144/0x15c
 sp : ffff80008160bc20
 x29: ffff80008160bc20 x28: ffffa967de7ea200 x27: 0000000000000000
 x26: ffff03ffc7bb18e8 x25: 0000000112be0f33 x24: 0000000000000001
 x23: ffffa967dd981888 x22: 0000000000000001 x21: ffffa967dc27166c
 x20: 0000000000000000 x19: ffffa967deae9920 x18: 0000000000000038
 x17: 0000000000000000 x16: 0000000000003ff1 x15: fffffffffffe9c68
 x14: ffffa967de815360 x13: 0000000000000669 x12: 0000000000000223
 x11: fffffffffffe9c68 x10: fffffffffffe9c30 x9 : 00000000fffff223
 x8 : ffffa967de815360 x7 : ffffa967de86d360 x6 : 00000000000019a4
 x5 : 000000000000bff4 x4 : 00000000fffff223 x3 : 0000000000000000
 x2 : 0000000000000000 x1 : 0000000000000000 x0 : ffff03ffc7266500
 Call trace:
  clk_branch_wait+0x144/0x15c
  clk_branch2_enable+0x30/0x40
  clk_core_enable+0xe8/0x284
  clk_enable+0x2c/0x4c
  ufshcd_setup_clocks+0x268/0x3d4
  ufshcd_ungate_work+0xc0/0x134
  process_one_work+0x1ec/0x53c
  worker_thread+0x298/0x408
  kthread+0x124/0x128
  ret_from_fork+0x10/0x20
 irq event stamp: 76
 hardirqs last  enabled at (75): [<ffffa967dcc9ced0>]
_raw_spin_unlock_irq+0x30/0x6c
 hardirqs last disabled at (76): [<ffffa967dc224250>]
clk_enable_lock+0x7c/0xf0
 softirqs last  enabled at (0): [<ffffa967dbb186c8>]
copy_process+0x650/0x21d8
 softirqs last disabled at (0): [<0000000000000000>] 0x0
 ---[ end trace 0000000000000000 ]---
 ufshcd-qcom 1d84000.ufshc: ufshcd_setup_clocks: core_clk prepare
enable failed, -16


Let me know if you need more logs or information.


> arch/arm64/boot/dts/qcom/sm8250.dtsi | 39 +++++++++++++++++++++-------
> 1 file changed, 30 insertions(+), 9 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi
> index a4e58ad731c3..33abd84aae53 100644
> --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi
> @@ -2198,21 +2198,42 @@ ufs_mem_hc: ufshc@1d84000 {
> <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
> <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
> <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
> - freq-table-hz =
> - <37500000 300000000>,
> - <0 0>,
> - <0 0>,
> - <37500000 300000000>,
> - <0 0>,
> - <0 0>,
> - <0 0>,
> - <0 0>;
> +
> + operating-points-v2 = <&ufs_opp_table>;
>
> interconnects = <&aggre1_noc MASTER_UFS_MEM 0 &mc_virt SLAVE_EBI_CH0 0>,
> <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_UFS_MEM_CFG 0>;
> interconnect-names = "ufs-ddr", "cpu-ufs";
>
> status = "disabled";
> +
> + ufs_opp_table: opp-table {
> + compatible = "operating-points-v2";
> +
> + opp-37500000 {
> + opp-hz = /bits/ 64 <37500000>,
> + /bits/ 64 <0>,
> + /bits/ 64 <0>,
> + /bits/ 64 <37500000>,
> + /bits/ 64 <0>,
> + /bits/ 64 <0>,
> + /bits/ 64 <0>,
> + /bits/ 64 <0>;
> + required-opps = <&rpmhpd_opp_low_svs>;
> + };
> +
> + opp-300000000 {
> + opp-hz = /bits/ 64 <300000000>,
> + /bits/ 64 <0>,
> + /bits/ 64 <0>,
> + /bits/ 64 <300000000>,
> + /bits/ 64 <0>,
> + /bits/ 64 <0>,
> + /bits/ 64 <0>,
> + /bits/ 64 <0>;
> + required-opps = <&rpmhpd_opp_nom>;
> + };
> + };
> };
>
> ufs_mem_phy: phy@1d87000 {

Best regards
--
Marek Szyprowski, PhD
Samsung R&D Institute Poland

2023-12-06 04:31:34

by Manivannan Sadhasivam

[permalink] [raw]
Subject: Re: [PATCH v7 5/5] arm64: dts: qcom: sm8250: Add OPP table support to UFSHC

On Tue, Dec 05, 2023 at 09:56:07PM +0100, Marek Szyprowski wrote:
> On 12.10.2023 19:21, Manivannan Sadhasivam wrote:
> > UFS host controller, when scaling gears, should choose appropriate
> > performance state of RPMh power domain controller along with clock
> > frequency. So let's add the OPP table support to specify both clock
> > frequency and RPMh performance states replacing the old "freq-table-hz"
> > property.
> >
> > Reviewed-by: Dmitry Baryshkov <[email protected]>
> > Signed-off-by: Manivannan Sadhasivam <[email protected]>
> > ---
>
>
> This patch landed in today's linux-next as commit 725be1d6318e ("arm64:
> dts: qcom: sm8250: Add OPP table support to UFSHC"). Unfortunately it
> breaks booting of my RB5 board with the following messages:
>

Thanks for reporting. The issue is due to a regression in the UFS OPP code and
I've already requested Bjorn [1] to drop these DTS patches until the driver fix
gets merged.

- Mani

[1] https://lore.kernel.org/linux-arm-msm/20231204120137.GE35383@thinkpad/

>  ufshcd-qcom 1d84000.ufshc: Adding to iommu group 5
>  ufshcd-qcom 1d84000.ufshc: freq-table-hz property not specified
>  ufshcd-qcom 1d84000.ufshc: ufshcd_populate_vreg: Unable to find
> vdd-hba-supply regulator, assuming enabled
>  ufshcd-qcom 1d84000.ufshc: freq-table-hz property not specified
>  ufshcd-qcom 1d84000.ufshc: ufshcd_populate_vreg: Unable to find
> vdd-hba-supply regulator, assuming enabled
>  scsi host0: ufshcd
>  ufshcd-qcom 1d84000.ufshc: UNIPRO clk freq 0 MHz not supported
>  ufshcd-qcom 1d84000.ufshc: cfg core clk ctrl failed
>  clk: Disabling unused clocks
>  ALSA device list:
>    No soundcards found.
>  Waiting 2 sec before mounting root device...
>  ufshcd-qcom 1d84000.ufshc: uic cmd 0x16 with arg3 0x0 completion timeout
>  ufshcd-qcom 1d84000.ufshc: Controller enable failed
>  ufshcd-qcom 1d84000.ufshc: Controller enable failed
>  ufshcd-qcom 1d84000.ufshc: Controller enable failed
>  ufshcd-qcom 1d84000.ufshc: Controller enable failed
>  ufshcd-qcom 1d84000.ufshc: link startup failed -110
>  ufshcd-qcom 1d84000.ufshc: UFS Host state=0
>  ufshcd-qcom 1d84000.ufshc: outstanding reqs=0x0 tasks=0x0
>  ufshcd-qcom 1d84000.ufshc: saved_err=0x0, saved_uic_err=0x0
>  ufshcd-qcom 1d84000.ufshc: Device power mode=1, UIC link state=0
>  ufshcd-qcom 1d84000.ufshc: PM in progress=0, sys. suspended=0
>  ufshcd-qcom 1d84000.ufshc: Auto BKOPS=0, Host self-block=0
>  ufshcd-qcom 1d84000.ufshc: Clk gate=1
>  ufshcd-qcom 1d84000.ufshc: last_hibern8_exit_tstamp at 0 us,
> hibern8_exit_cnt=0
>  ufshcd-qcom 1d84000.ufshc: last intr at 2889168 us, last intr status=0x400
>  ufshcd-qcom 1d84000.ufshc: error handling flags=0x0, req. abort count=0
>  ufshcd-qcom 1d84000.ufshc: hba->ufs_version=0x300, Host
> capabilities=0x1587031f, caps=0x12cf
>  ufshcd-qcom 1d84000.ufshc: quirks=0x80000, dev. quirks=0x0
>  host_regs: 00000000: 1587031f 00000000 00000300 00000000
>  host_regs: 00000010: 01000000 00010217 00000000 00000000
>  host_regs: 00000020: 00000000 00000000 00000000 00000000
>  host_regs: 00000030: 00000008 00000000 00000000 00000000
>  host_regs: 00000040: 00000000 00000000 00000000 00000000
>  host_regs: 00000050: 00000000 00000000 00000000 00000000
>  host_regs: 00000060: 00000000 00000000 00000000 00000000
>  host_regs: 00000070: 00000000 00000000 00000000 00000000
>  host_regs: 00000080: 00000000 00000000 00000000 00000000
>  host_regs: 00000090: 00000000 00000001 00000000 00000000
>  ufshcd-qcom 1d84000.ufshc: No record of pa_err
>  ufshcd-qcom 1d84000.ufshc: No record of dl_err
>  ufshcd-qcom 1d84000.ufshc: No record of nl_err
>  ufshcd-qcom 1d84000.ufshc: No record of tl_err
>  ufshcd-qcom 1d84000.ufshc: No record of dme_err
>  ufshcd-qcom 1d84000.ufshc: No record of auto_hibern8_err
>  ufshcd-qcom 1d84000.ufshc: No record of fatal_err
>  ufshcd-qcom 1d84000.ufshc: link_startup_fail[0] = 0xffffff92 at 3663462 us
>  ufshcd-qcom 1d84000.ufshc: link_startup_fail: total cnt=1
>  ufshcd-qcom 1d84000.ufshc: No record of resume_fail
>  ufshcd-qcom 1d84000.ufshc: No record of suspend_fail
>  ufshcd-qcom 1d84000.ufshc: No record of wlun resume_fail
>  ufshcd-qcom 1d84000.ufshc: No record of wlun suspend_fail
>  ufshcd-qcom 1d84000.ufshc: No record of dev_reset
>  ufshcd-qcom 1d84000.ufshc: No record of host_reset
>  ufshcd-qcom 1d84000.ufshc: No record of task_abort
>  HCI Vendor Specific Registers 00000000: 0000012c 00000000 00000000
> 00000000
>  HCI Vendor Specific Registers 00000010: 00000042 00000000 00000001
> 1c00052c
>  HCI Vendor Specific Registers 00000020: 3f011300 40020000 00000000
> 00000000
>  HCI Vendor Specific Registers 00000030: 00000000 00000000 00000000
> 00000000
>  UFS_UFS_DBG_RD_REG_OCSC 00000000: 00000000 00000000 00000000 00000000
>  UFS_UFS_DBG_RD_REG_OCSC 00000010: 00000000 00000000 00000000 00000000
>  UFS_UFS_DBG_RD_REG_OCSC 00000020: 00000000 00000000 00000000 00000000
>  UFS_UFS_DBG_RD_REG_OCSC 00000030: 00000000 00000000 00000000 00000000
>  UFS_UFS_DBG_RD_REG_OCSC 00000040: 00000000 00000000 00000000 00000000
>  UFS_UFS_DBG_RD_REG_OCSC 00000050: 00000000 00000000 00000000 00000000
>  UFS_UFS_DBG_RD_REG_OCSC 00000060: 00000000 00000000 00000000 00000000
>  UFS_UFS_DBG_RD_REG_OCSC 00000070: 00000000 00000000 00000000 00000000
>  UFS_UFS_DBG_RD_REG_OCSC 00000080: 00000000 00000000 00000000 00000000
>  UFS_UFS_DBG_RD_REG_OCSC 00000090: 00000000 00000000 00000000 00000000
>  UFS_UFS_DBG_RD_REG_OCSC 000000a0: 00000000 00000000 00000000 00000000
>  UFS_UFS_DBG_RD_EDTL_RAM 00000000: 00000000 7147f7fd 47857989 b7556f16
>  UFS_UFS_DBG_RD_EDTL_RAM 00000010: ad69b114 7cd5fd55 41d57796 0e55e717
>  UFS_UFS_DBG_RD_EDTL_RAM 00000020: 04558745 efc573b5 4f35f49b b2697d16
>  UFS_UFS_DBG_RD_EDTL_RAM 00000030: 5c7563d5 7755f4d6 cf65dd90 6591d535
>  UFS_UFS_DBG_RD_EDTL_RAM 00000040: 4151f597 ffaf75a9 57442485 f7654511
>  UFS_UFS_DBG_RD_EDTL_RAM 00000050: fc57e046 ff57f5b5 c7c53417 adb56f55
>  UFS_UFS_DBG_RD_EDTL_RAM 00000060: 9b753f4c 5155a115 245525f1 77755d51
>  UFS_UFS_DBG_RD_EDTL_RAM 00000070: 5791ffdf 77555756 7cd5b941 431ce192
>  UFS_UFS_DBG_RD_DESC_RAM 00000000: 7dfffedf 001fbffb ff7fffff 003ffffd
>  UFS_UFS_DBG_RD_DESC_RAM 00000010: 7f3dfff5 003fffff 7ffdfff3 0017fff7
>  UFS_UFS_DBG_RD_DESC_RAM 00000020: 3fdd595f 003ff5b7 ffffdfdf 003f77f7
>  UFS_UFS_DBG_RD_DESC_RAM 00000030: fffff7d7 003f75f7 7fffffff 0037ffff
>  UFS_UFS_DBG_RD_DESC_RAM 00000040: fdff7f7f 003f57df fdfeffbf 003ffff7
>  UFS_UFS_DBG_RD_DESC_RAM 00000050: 7d7d7fff 00379d7f 7ffd7fff 001f3fff
>  UFS_UFS_DBG_RD_DESC_RAM 00000060: 7f7fdeff 003fffd5 f7f7fffd 003fffff
>  UFS_UFS_DBG_RD_DESC_RAM 00000070: 777ffd7d 003ffd75 ff7ffffd 003f7ffd
>  UFS_UFS_DBG_RD_DESC_RAM 00000080: ff15fddf 003edfd7 df5ffff7 003fffdf
>  UFS_UFS_DBG_RD_DESC_RAM 00000090: ffe57f5f 003fbff7 ddd7ff75 003f7fff
>  UFS_UFS_DBG_RD_DESC_RAM 000000a0: fd4ffffd 003dddff eefffff7 003fbfff
>  UFS_UFS_DBG_RD_DESC_RAM 000000b0: 67fffffd 001ff7fd bdd75f7f 0031bfff
>  UFS_UFS_DBG_RD_DESC_RAM 000000c0: ffdddf75 003fff5d 7f5fffdd 002f7fdf
>  UFS_UFS_DBG_RD_DESC_RAM 000000d0: ff7d5ffd 0037fdff df675fd5 001ffbdf
>  UFS_UFS_DBG_RD_DESC_RAM 000000e0: b5ff7dff 00337ffc ff7ff7fb 003ffff7
>  UFS_UFS_DBG_RD_DESC_RAM 000000f0: 5ffdffdd 001ddfff 75ffddff 003fffff
>  UFS_UFS_DBG_RD_DESC_RAM 00000100: ff5f5fdf 003d37bf ff77dfff 0017edb7
>  UFS_UFS_DBG_RD_DESC_RAM 00000110: ff7ff7ff 003ffd7f ff5f7fdd 003f3fd7
>  UFS_UFS_DBG_RD_DESC_RAM 00000120: 7fffffdf 003ff5d9 55ffffdf 003f79d5
>  UFS_UFS_DBG_RD_DESC_RAM 00000130: d5ffe7f5 002767fe ffdd75df 003d7fdf
>  UFS_UFS_DBG_RD_DESC_RAM 00000140: 7fff77ff 003dff5f 7d7ff7ff 002f7fff
>  UFS_UFS_DBG_RD_DESC_RAM 00000150: fdff7ddf 003fe7dd 5df77ddd 0037f7ff
>  UFS_UFS_DBG_RD_DESC_RAM 00000160: f7f16977 003f9fdf 5775ff77 00357ff5
>  UFS_UFS_DBG_RD_DESC_RAM 00000170: 7ffdfffb 003dff5f 7f7f77f7 003fffff
>  UFS_UFS_DBG_RD_DESC_RAM 00000180: 57dff7df 003dffff fffdd7ff 001efffd
>  UFS_UFS_DBG_RD_DESC_RAM 00000190: 7dffffed 003f7fce 77d9f7ff 001fdddd
>  UFS_UFS_DBG_RD_DESC_RAM 000001a0: ddffdffd 001fd57d 7f7ff777 003f78dd
>  UFS_UFS_DBG_RD_DESC_RAM 000001b0: d5eff77f 0037dfdf ed7d77ff 003ffffd
>  UFS_UFS_DBG_RD_DESC_RAM 000001c0: cf7fdfff 001f5f7e ffffffff 003f57df
>  UFS_UFS_DBG_RD_DESC_RAM 000001d0: fdfffffd 003f7dff 556ffddf 003fdd7f
>  UFS_UFS_DBG_RD_DESC_RAM 000001e0: fdff71df 003e7fff ff3f7fd7 0037f77b
>  UFS_UFS_DBG_RD_DESC_RAM 000001f0: 7f7f7677 00355fdf 7feffdff 0037ffff
>  UFS_UFS_DBG_RD_PRDT_RAM 00000000: d1700001 0000192c 3d9edf71 00075d51
>  UFS_UFS_DBG_RD_PRDT_RAM 00000010: 4561073f 0000415d ddde6dd9 000ff55f
>  UFS_UFS_DBG_RD_PRDT_RAM 00000020: adb7185f 000df971 579caffd 000de54d
>  UFS_UFS_DBG_RD_PRDT_RAM 00000030: 45e55747 00057559 7f5e5dbd 000377df
>  UFS_UFS_DBG_RD_PRDT_RAM 00000040: dd175467 0007dc9c 4e775d77 0007555f
>  UFS_UFS_DBG_RD_PRDT_RAM 00000050: 1f15dd77 000d195d f1c9e535 0007b75f
>  UFS_UFS_DBG_RD_PRDT_RAM 00000060: 15bd75f3 0007675f dfd59d77 00057b5c
>  UFS_UFS_DBG_RD_PRDT_RAM 00000070: d4f09dee 00017d39 52857d56 000c6ddd
>  UFS_UFS_DBG_RD_PRDT_RAM 00000080: c333fcd6 000545df 1d57f51d 000577e9
>  UFS_UFS_DBG_RD_PRDT_RAM 00000090: 9f83d45d 00055d18 d4e7d7ee 000713df
>  UFS_UFS_DBG_RD_PRDT_RAM 000000a0: fdfe39d7 000754df d54f5d77 000746f1
>  UFS_UFS_DBG_RD_PRDT_RAM 000000b0: 5a40c5f5 000c45d4 17471fe3 000e9d1d
>  UFS_UFS_DBG_RD_PRDT_RAM 000000c0: 1747dd5f 00074577 d540d75d 00044d67
>  UFS_UFS_DBG_RD_PRDT_RAM 000000d0: de3545d3 000c4757 5f845115 00063795
>  UFS_UFS_DBG_RD_PRDT_RAM 000000e0: d15d776c 000c7fd5 1f5f5d75 00067d75
>  UFS_UFS_DBG_RD_PRDT_RAM 000000f0: d71d4c7d 0007bd13 7557d77d 000355df
>  UFS_DBG_RD_REG_UAWM 00000000: 00000000 0fe00000 00000004 f4000102
>  UFS_DBG_RD_REG_UARM 00000000: 00000000 00000000 00000001 00000001
>  UFS_DBG_RD_REG_TXUC 00000000: 00000000 00000000 00000000 00000000
>  UFS_DBG_RD_REG_TXUC 00000010: 00000000 00000000 00000000 00000000
>  UFS_DBG_RD_REG_TXUC 00000020: 00000000 00000000 00000000 00000000
>  UFS_DBG_RD_REG_TXUC 00000030: 00000000 00000000 00000000 00000000
>  UFS_DBG_RD_REG_TXUC 00000040: 00000000 00000000 00000000 00000000
>  UFS_DBG_RD_REG_TXUC 00000050: 00000000 00000000 00000000 00000000
>  UFS_DBG_RD_REG_TXUC 00000060: 00000000 00000000 00000000 00000000
>  UFS_DBG_RD_REG_TXUC 00000070: 00000000 00000000 00000000 00000000
>  UFS_DBG_RD_REG_TXUC 00000080: 00000000 00000000 00000000 00000000
>  UFS_DBG_RD_REG_TXUC 00000090: 00000000 00000000 00000000 00000000
>  UFS_DBG_RD_REG_TXUC 000000a0: 00000000 00000000 00000000 00000000
>  UFS_DBG_RD_REG_TXUC 000000b0: 00000001 00000000 00000000 00000004
>  UFS_DBG_RD_REG_RXUC 00000000: 00000000 00000000 00000000 00000004
>  UFS_DBG_RD_REG_RXUC 00000010: 00000000 00000000 00000000 00000000
>  UFS_DBG_RD_REG_RXUC 00000020: 00000000 00000000 00000000 00000000
>  UFS_DBG_RD_REG_RXUC 00000030: 00000000 00000000 00000000 00000000
>  UFS_DBG_RD_REG_RXUC 00000040: 00000000 00000000 00000000 00000000
>  UFS_DBG_RD_REG_RXUC 00000050: 00000000 00000000 00000000 00000001
>  UFS_DBG_RD_REG_RXUC 00000060: 00000000 00000000 00000004
>  UFS_DBG_RD_REG_DFC 00000000: 00000000 00000000 00000000 00000000
>  UFS_DBG_RD_REG_DFC 00000010: 00000000 00000000 00000000 00000000
>  UFS_DBG_RD_REG_DFC 00000020: 00000000 00000000 00000000 00000000
>  UFS_DBG_RD_REG_DFC 00000030: 00000000 00000000 00000000 00000000
>  UFS_DBG_RD_REG_DFC 00000040: ffffffff 00000000 00000000
>  UFS_DBG_RD_REG_TRLUT 00000000: 00000000 00000000 00000000 00000000
>  UFS_DBG_RD_REG_TRLUT 00000010: 00000000 00000000 00000000 00000000
>  UFS_DBG_RD_REG_TRLUT 00000020: 00000000 00000000 00000000 00000000
>  UFS_DBG_RD_REG_TRLUT 00000030: 00000000 00000000 00000000 00000000
>  UFS_DBG_RD_REG_TRLUT 00000040: 00000000 00000000 00000000 00000000
>  UFS_DBG_RD_REG_TRLUT 00000050: 00000000 00000000 00000000 00000000
>  UFS_DBG_RD_REG_TRLUT 00000060: 00000000 00000000 00000000 00000000
>  UFS_DBG_RD_REG_TRLUT 00000070: 00000000 00000000 00000000 00000000
>  UFS_DBG_RD_REG_TRLUT 00000080: 00000000 00000000
>  UFS_DBG_RD_REG_TMRLUT 00000000: 00000000 00000000 00000000 00000000
>  UFS_DBG_RD_REG_TMRLUT 00000010: 00000000 00000000 00000000 00000000
>  UFS_DBG_RD_REG_TMRLUT 00000020: 00000000
>  ------------[ cut here ]------------
>  gcc_ufs_phy_axi_clk status stuck at 'off'
>  WARNING: CPU: 3 PID: 103 at drivers/clk/qcom/clk-branch.c:86
> clk_branch_wait+0x144/0x15c
>  Modules linked in:
>  CPU: 3 PID: 103 Comm: kworker/u17:0 Not tainted
> 6.7.0-rc4-next-20231205 #14278
>  Hardware name: Qualcomm Technologies, Inc. Robotics RB5 (DT)
>  Workqueue: ufs_clk_gating_0 ufshcd_ungate_work
>  pstate: 604000c5 (nZCv daIF +PAN -UAO -TCO -DIT -SSBS BTYPE=--)
>  pc : clk_branch_wait+0x144/0x15c
>  lr : clk_branch_wait+0x144/0x15c
>  sp : ffff80008160bc20
>  x29: ffff80008160bc20 x28: ffffa967de7ea200 x27: 0000000000000000
>  x26: ffff03ffc7bb18e8 x25: 0000000112be0f33 x24: 0000000000000001
>  x23: ffffa967dd981888 x22: 0000000000000001 x21: ffffa967dc27166c
>  x20: 0000000000000000 x19: ffffa967deae9920 x18: 0000000000000038
>  x17: 0000000000000000 x16: 0000000000003ff1 x15: fffffffffffe9c68
>  x14: ffffa967de815360 x13: 0000000000000669 x12: 0000000000000223
>  x11: fffffffffffe9c68 x10: fffffffffffe9c30 x9 : 00000000fffff223
>  x8 : ffffa967de815360 x7 : ffffa967de86d360 x6 : 00000000000019a4
>  x5 : 000000000000bff4 x4 : 00000000fffff223 x3 : 0000000000000000
>  x2 : 0000000000000000 x1 : 0000000000000000 x0 : ffff03ffc7266500
>  Call trace:
>   clk_branch_wait+0x144/0x15c
>   clk_branch2_enable+0x30/0x40
>   clk_core_enable+0xe8/0x284
>   clk_enable+0x2c/0x4c
>   ufshcd_setup_clocks+0x268/0x3d4
>   ufshcd_ungate_work+0xc0/0x134
>   process_one_work+0x1ec/0x53c
>   worker_thread+0x298/0x408
>   kthread+0x124/0x128
>   ret_from_fork+0x10/0x20
>  irq event stamp: 76
>  hardirqs last  enabled at (75): [<ffffa967dcc9ced0>]
> _raw_spin_unlock_irq+0x30/0x6c
>  hardirqs last disabled at (76): [<ffffa967dc224250>]
> clk_enable_lock+0x7c/0xf0
>  softirqs last  enabled at (0): [<ffffa967dbb186c8>]
> copy_process+0x650/0x21d8
>  softirqs last disabled at (0): [<0000000000000000>] 0x0
>  ---[ end trace 0000000000000000 ]---
>  ufshcd-qcom 1d84000.ufshc: ufshcd_setup_clocks: core_clk prepare
> enable failed, -16
>
>
> Let me know if you need more logs or information.
>
>
> > arch/arm64/boot/dts/qcom/sm8250.dtsi | 39 +++++++++++++++++++++-------
> > 1 file changed, 30 insertions(+), 9 deletions(-)
> >
> > diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi
> > index a4e58ad731c3..33abd84aae53 100644
> > --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi
> > +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi
> > @@ -2198,21 +2198,42 @@ ufs_mem_hc: ufshc@1d84000 {
> > <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
> > <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
> > <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
> > - freq-table-hz =
> > - <37500000 300000000>,
> > - <0 0>,
> > - <0 0>,
> > - <37500000 300000000>,
> > - <0 0>,
> > - <0 0>,
> > - <0 0>,
> > - <0 0>;
> > +
> > + operating-points-v2 = <&ufs_opp_table>;
> >
> > interconnects = <&aggre1_noc MASTER_UFS_MEM 0 &mc_virt SLAVE_EBI_CH0 0>,
> > <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_UFS_MEM_CFG 0>;
> > interconnect-names = "ufs-ddr", "cpu-ufs";
> >
> > status = "disabled";
> > +
> > + ufs_opp_table: opp-table {
> > + compatible = "operating-points-v2";
> > +
> > + opp-37500000 {
> > + opp-hz = /bits/ 64 <37500000>,
> > + /bits/ 64 <0>,
> > + /bits/ 64 <0>,
> > + /bits/ 64 <37500000>,
> > + /bits/ 64 <0>,
> > + /bits/ 64 <0>,
> > + /bits/ 64 <0>,
> > + /bits/ 64 <0>;
> > + required-opps = <&rpmhpd_opp_low_svs>;
> > + };
> > +
> > + opp-300000000 {
> > + opp-hz = /bits/ 64 <300000000>,
> > + /bits/ 64 <0>,
> > + /bits/ 64 <0>,
> > + /bits/ 64 <300000000>,
> > + /bits/ 64 <0>,
> > + /bits/ 64 <0>,
> > + /bits/ 64 <0>,
> > + /bits/ 64 <0>;
> > + required-opps = <&rpmhpd_opp_nom>;
> > + };
> > + };
> > };
> >
> > ufs_mem_phy: phy@1d87000 {
>
> Best regards
> --
> Marek Szyprowski, PhD
> Samsung R&D Institute Poland
>

--
மணிவண்ணன் சதாசிவம்