Allow userspace to configure cycle count threshold through
perf_event_attr config. The last high 12-bit of config value is used to
store the cycle count threshold.
Signed-off-by: Wei-Ning Huang <[email protected]>
---
drivers/hwtracing/coresight/coresight-etm4x-core.c | 6 +++++-
include/linux/coresight-pmu.h | 14 ++++++++------
tools/include/linux/coresight-pmu.h | 14 ++++++++------
3 files changed, 21 insertions(+), 13 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c
index 77b0271ce6eb..155441668b4a 100644
--- a/drivers/hwtracing/coresight/coresight-etm4x-core.c
+++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c
@@ -645,6 +645,7 @@ static int etm4_parse_event_config(struct coresight_device *csdev,
struct perf_event_attr *attr = &event->attr;
unsigned long cfg_hash;
int preset;
+ u64 cyc_threadhold;
/* Clear configuration from previous run */
memset(config, 0, sizeof(struct etmv4_config));
@@ -667,7 +668,10 @@ static int etm4_parse_event_config(struct coresight_device *csdev,
if (attr->config & BIT(ETM_OPT_CYCACC)) {
config->cfg |= TRCCONFIGR_CCI;
/* TRM: Must program this for cycacc to work */
- config->ccctlr = ETM_CYC_THRESHOLD_DEFAULT;
+ cyc_threshold = ((attr->config >> ETM_OPT_CYC_THRESHOLD_SHIFT) &
+ ETM_OPT_CYC_THRESHOLD_MASK;
+ config->ccctlr = cyc_threshold ? cyc_threshold :
+ ETM_CYC_THRESHOLD_DEFAULT;
}
if (attr->config & BIT(ETM_OPT_TS)) {
/*
diff --git a/include/linux/coresight-pmu.h b/include/linux/coresight-pmu.h
index 51ac441a37c3..14f48658ff1c 100644
--- a/include/linux/coresight-pmu.h
+++ b/include/linux/coresight-pmu.h
@@ -29,12 +29,14 @@
* ETMv3.5/PTM doesn't define ETMCR config bits with prefix "ETM3_" and
* directly use below macros as config bits.
*/
-#define ETM_OPT_BRANCH_BROADCAST 8
-#define ETM_OPT_CYCACC 12
-#define ETM_OPT_CTXTID 14
-#define ETM_OPT_CTXTID2 15
-#define ETM_OPT_TS 28
-#define ETM_OPT_RETSTK 29
+#define ETM_OPT_BRANCH_BROADCAST 8
+#define ETM_OPT_CYCACC 12
+#define ETM_OPT_CTXTID 14
+#define ETM_OPT_CTXTID2 15
+#define ETM_OPT_TS 28
+#define ETM_OPT_RETSTK 29
+#define ETM_OPT_CYC_THRESHOLD_SHIFT 52
+#define ETM_OPT_CYC_THRESHOLD_MASK 0xfff
/* ETMv4 CONFIGR programming bits for the ETM OPTs */
#define ETM4_CFG_BIT_BB 3
diff --git a/tools/include/linux/coresight-pmu.h b/tools/include/linux/coresight-pmu.h
index 51ac441a37c3..14f48658ff1c 100644
--- a/tools/include/linux/coresight-pmu.h
+++ b/tools/include/linux/coresight-pmu.h
@@ -29,12 +29,14 @@
* ETMv3.5/PTM doesn't define ETMCR config bits with prefix "ETM3_" and
* directly use below macros as config bits.
*/
-#define ETM_OPT_BRANCH_BROADCAST 8
-#define ETM_OPT_CYCACC 12
-#define ETM_OPT_CTXTID 14
-#define ETM_OPT_CTXTID2 15
-#define ETM_OPT_TS 28
-#define ETM_OPT_RETSTK 29
+#define ETM_OPT_BRANCH_BROADCAST 8
+#define ETM_OPT_CYCACC 12
+#define ETM_OPT_CTXTID 14
+#define ETM_OPT_CTXTID2 15
+#define ETM_OPT_TS 28
+#define ETM_OPT_RETSTK 29
+#define ETM_OPT_CYC_THRESHOLD_SHIFT 52
+#define ETM_OPT_CYC_THRESHOLD_MASK 0xfff
/* ETMv4 CONFIGR programming bits for the ETM OPTs */
#define ETM4_CFG_BIT_BB 3
--
2.42.0.655.g421f12c284-goog
On 19/10/2023 09:23, Wei-Ning Huang wrote:
> Allow userspace to configure cycle count threshold through
> perf_event_attr config. The last high 12-bit of config value is used to
> store the cycle count threshold.
>
We have queued the support already in coreisght next tree,
patches posted here [0]
[0] -
https://lore.kernel.org/r/[email protected]
Suzuki
> Signed-off-by: Wei-Ning Huang <[email protected]>
> ---
> drivers/hwtracing/coresight/coresight-etm4x-core.c | 6 +++++-
> include/linux/coresight-pmu.h | 14 ++++++++------
> tools/include/linux/coresight-pmu.h | 14 ++++++++------
> 3 files changed, 21 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c
> index 77b0271ce6eb..155441668b4a 100644
> --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c
> +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c
> @@ -645,6 +645,7 @@ static int etm4_parse_event_config(struct coresight_device *csdev,
> struct perf_event_attr *attr = &event->attr;
> unsigned long cfg_hash;
> int preset;
> + u64 cyc_threadhold;
>
> /* Clear configuration from previous run */
> memset(config, 0, sizeof(struct etmv4_config));
> @@ -667,7 +668,10 @@ static int etm4_parse_event_config(struct coresight_device *csdev,
> if (attr->config & BIT(ETM_OPT_CYCACC)) {
> config->cfg |= TRCCONFIGR_CCI;
> /* TRM: Must program this for cycacc to work */
> - config->ccctlr = ETM_CYC_THRESHOLD_DEFAULT;
> + cyc_threshold = ((attr->config >> ETM_OPT_CYC_THRESHOLD_SHIFT) &
> + ETM_OPT_CYC_THRESHOLD_MASK;
> + config->ccctlr = cyc_threshold ? cyc_threshold :
> + ETM_CYC_THRESHOLD_DEFAULT;
> }
> if (attr->config & BIT(ETM_OPT_TS)) {
> /*
> diff --git a/include/linux/coresight-pmu.h b/include/linux/coresight-pmu.h
> index 51ac441a37c3..14f48658ff1c 100644
> --- a/include/linux/coresight-pmu.h
> +++ b/include/linux/coresight-pmu.h
> @@ -29,12 +29,14 @@
> * ETMv3.5/PTM doesn't define ETMCR config bits with prefix "ETM3_" and
> * directly use below macros as config bits.
> */
> -#define ETM_OPT_BRANCH_BROADCAST 8
> -#define ETM_OPT_CYCACC 12
> -#define ETM_OPT_CTXTID 14
> -#define ETM_OPT_CTXTID2 15
> -#define ETM_OPT_TS 28
> -#define ETM_OPT_RETSTK 29
> +#define ETM_OPT_BRANCH_BROADCAST 8
> +#define ETM_OPT_CYCACC 12
> +#define ETM_OPT_CTXTID 14
> +#define ETM_OPT_CTXTID2 15
> +#define ETM_OPT_TS 28
> +#define ETM_OPT_RETSTK 29
> +#define ETM_OPT_CYC_THRESHOLD_SHIFT 52
> +#define ETM_OPT_CYC_THRESHOLD_MASK 0xfff
>
> /* ETMv4 CONFIGR programming bits for the ETM OPTs */
> #define ETM4_CFG_BIT_BB 3
> diff --git a/tools/include/linux/coresight-pmu.h b/tools/include/linux/coresight-pmu.h
> index 51ac441a37c3..14f48658ff1c 100644
> --- a/tools/include/linux/coresight-pmu.h
> +++ b/tools/include/linux/coresight-pmu.h
> @@ -29,12 +29,14 @@
> * ETMv3.5/PTM doesn't define ETMCR config bits with prefix "ETM3_" and
> * directly use below macros as config bits.
> */
> -#define ETM_OPT_BRANCH_BROADCAST 8
> -#define ETM_OPT_CYCACC 12
> -#define ETM_OPT_CTXTID 14
> -#define ETM_OPT_CTXTID2 15
> -#define ETM_OPT_TS 28
> -#define ETM_OPT_RETSTK 29
> +#define ETM_OPT_BRANCH_BROADCAST 8
> +#define ETM_OPT_CYCACC 12
> +#define ETM_OPT_CTXTID 14
> +#define ETM_OPT_CTXTID2 15
> +#define ETM_OPT_TS 28
> +#define ETM_OPT_RETSTK 29
> +#define ETM_OPT_CYC_THRESHOLD_SHIFT 52
> +#define ETM_OPT_CYC_THRESHOLD_MASK 0xfff
>
> /* ETMv4 CONFIGR programming bits for the ETM OPTs */
> #define ETM4_CFG_BIT_BB 3
Hi Wei-Ning,
kernel test robot noticed the following build errors:
[auto build test ERROR on soc/for-next]
[also build test ERROR on linus/master v6.6-rc7]
[cannot apply to next-20231023]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Wei-Ning-Huang/coresight-etm4x-Allow-configuring-cycle-count-threshold/20231019-162600
base: https://git.kernel.org/pub/scm/linux/kernel/git/soc/soc.git for-next
patch link: https://lore.kernel.org/r/20231019082357.1505047-1-wnhuang%40google.com
patch subject: [PATCH] coresight: etm4x: Allow configuring cycle count threshold
config: arm64-randconfig-001-20231023 (https://download.01.org/0day-ci/archive/20231023/[email protected]/config)
compiler: aarch64-linux-gcc (GCC) 13.2.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20231023/[email protected]/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <[email protected]>
| Closes: https://lore.kernel.org/oe-kbuild-all/[email protected]/
All error/warnings (new ones prefixed by >>):
drivers/hwtracing/coresight/coresight-etm4x-core.c: In function 'etm4_parse_event_config':
>> drivers/hwtracing/coresight/coresight-etm4x-core.c:671:17: error: 'cyc_threshold' undeclared (first use in this function); did you mean 'cyc_threadhold'?
671 | cyc_threshold = ((attr->config >> ETM_OPT_CYC_THRESHOLD_SHIFT) &
| ^~~~~~~~~~~~~
| cyc_threadhold
drivers/hwtracing/coresight/coresight-etm4x-core.c:671:17: note: each undeclared identifier is reported only once for each function it appears in
>> drivers/hwtracing/coresight/coresight-etm4x-core.c:672:60: error: expected ')' before ';' token
672 | ETM_OPT_CYC_THRESHOLD_MASK;
| ^
drivers/hwtracing/coresight/coresight-etm4x-core.c:671:33: note: to match this '('
671 | cyc_threshold = ((attr->config >> ETM_OPT_CYC_THRESHOLD_SHIFT) &
| ^
>> drivers/hwtracing/coresight/coresight-etm4x-core.c:674:60: error: expected ';' before '}' token
674 | ETM_CYC_THRESHOLD_DEFAULT;
| ^
| ;
675 | }
| ~
>> drivers/hwtracing/coresight/coresight-etm4x-core.c:648:13: warning: unused variable 'cyc_threadhold' [-Wunused-variable]
648 | u64 cyc_threadhold;
| ^~~~~~~~~~~~~~
vim +671 drivers/hwtracing/coresight/coresight-etm4x-core.c
638
639 static int etm4_parse_event_config(struct coresight_device *csdev,
640 struct perf_event *event)
641 {
642 int ret = 0;
643 struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
644 struct etmv4_config *config = &drvdata->config;
645 struct perf_event_attr *attr = &event->attr;
646 unsigned long cfg_hash;
647 int preset;
> 648 u64 cyc_threadhold;
649
650 /* Clear configuration from previous run */
651 memset(config, 0, sizeof(struct etmv4_config));
652
653 if (attr->exclude_kernel)
654 config->mode = ETM_MODE_EXCL_KERN;
655
656 if (attr->exclude_user)
657 config->mode = ETM_MODE_EXCL_USER;
658
659 /* Always start from the default config */
660 etm4_set_default_config(config);
661
662 /* Configure filters specified on the perf cmd line, if any. */
663 ret = etm4_set_event_filters(drvdata, event);
664 if (ret)
665 goto out;
666
667 /* Go from generic option to ETMv4 specifics */
668 if (attr->config & BIT(ETM_OPT_CYCACC)) {
669 config->cfg |= TRCCONFIGR_CCI;
670 /* TRM: Must program this for cycacc to work */
> 671 cyc_threshold = ((attr->config >> ETM_OPT_CYC_THRESHOLD_SHIFT) &
> 672 ETM_OPT_CYC_THRESHOLD_MASK;
673 config->ccctlr = cyc_threshold ? cyc_threshold :
> 674 ETM_CYC_THRESHOLD_DEFAULT;
675 }
676 if (attr->config & BIT(ETM_OPT_TS)) {
677 /*
678 * Configure timestamps to be emitted at regular intervals in
679 * order to correlate instructions executed on different CPUs
680 * (CPU-wide trace scenarios).
681 */
682 ret = etm4_config_timestamp_event(drvdata);
683
684 /*
685 * No need to go further if timestamp intervals can't
686 * be configured.
687 */
688 if (ret)
689 goto out;
690
691 /* bit[11], Global timestamp tracing bit */
692 config->cfg |= TRCCONFIGR_TS;
693 }
694
695 /* Only trace contextID when runs in root PID namespace */
696 if ((attr->config & BIT(ETM_OPT_CTXTID)) &&
697 task_is_in_init_pid_ns(current))
698 /* bit[6], Context ID tracing bit */
699 config->cfg |= TRCCONFIGR_CID;
700
701 /*
702 * If set bit ETM_OPT_CTXTID2 in perf config, this asks to trace VMID
703 * for recording CONTEXTIDR_EL2. Do not enable VMID tracing if the
704 * kernel is not running in EL2.
705 */
706 if (attr->config & BIT(ETM_OPT_CTXTID2)) {
707 if (!is_kernel_in_hyp_mode()) {
708 ret = -EINVAL;
709 goto out;
710 }
711 /* Only trace virtual contextID when runs in root PID namespace */
712 if (task_is_in_init_pid_ns(current))
713 config->cfg |= TRCCONFIGR_VMID | TRCCONFIGR_VMIDOPT;
714 }
715
716 /* return stack - enable if selected and supported */
717 if ((attr->config & BIT(ETM_OPT_RETSTK)) && drvdata->retstack)
718 /* bit[12], Return stack enable bit */
719 config->cfg |= TRCCONFIGR_RS;
720
721 /*
722 * Set any selected configuration and preset.
723 *
724 * This extracts the values of PMU_FORMAT_ATTR(configid) and PMU_FORMAT_ATTR(preset)
725 * in the perf attributes defined in coresight-etm-perf.c.
726 * configid uses bits 63:32 of attr->config2, preset uses bits 3:0 of attr->config.
727 * A zero configid means no configuration active, preset = 0 means no preset selected.
728 */
729 if (attr->config2 & GENMASK_ULL(63, 32)) {
730 cfg_hash = (u32)(attr->config2 >> 32);
731 preset = attr->config & 0xF;
732 ret = cscfg_csdev_enable_active_config(csdev, cfg_hash, preset);
733 }
734
735 /* branch broadcast - enable if selected and supported */
736 if (attr->config & BIT(ETM_OPT_BRANCH_BROADCAST)) {
737 if (!drvdata->trcbb) {
738 /*
739 * Missing BB support could cause silent decode errors
740 * so fail to open if it's not supported.
741 */
742 ret = -EINVAL;
743 goto out;
744 } else {
745 config->cfg |= BIT(ETM4_CFG_BIT_BB);
746 }
747 }
748
749 out:
750 return ret;
751 }
752
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki