Using "ANDES" rather than "ANDESTECH" to unify the naming
convention with OpenSBI and U-Boot, and reduce the number
of characters per line.
Signed-off-by: Yu Chien Peter Lin <[email protected]>
Reviewed-by: Charles Ci-Jyun Wu <[email protected]>
Reviewed-by: Leo Yu-Chi Liang <[email protected]>
---
Changes v1 -> v2:
- No change
---
arch/riscv/errata/andes/errata.c | 10 +++++-----
arch/riscv/include/asm/errata_list.h | 4 ++--
arch/riscv/include/asm/vendorid_list.h | 2 +-
arch/riscv/kernel/alternative.c | 2 +-
4 files changed, 9 insertions(+), 9 deletions(-)
diff --git a/arch/riscv/errata/andes/errata.c b/arch/riscv/errata/andes/errata.c
index 197db68cc8da..d2e1abcac967 100644
--- a/arch/riscv/errata/andes/errata.c
+++ b/arch/riscv/errata/andes/errata.c
@@ -18,9 +18,9 @@
#include <asm/sbi.h>
#include <asm/vendorid_list.h>
-#define ANDESTECH_AX45MP_MARCHID 0x8000000000008a45UL
-#define ANDESTECH_AX45MP_MIMPID 0x500UL
-#define ANDESTECH_SBI_EXT_ANDES 0x0900031E
+#define ANDES_AX45MP_MARCHID 0x8000000000008a45UL
+#define ANDES_AX45MP_MIMPID 0x500UL
+#define ANDES_SBI_EXT_ANDES 0x0900031E
#define ANDES_SBI_EXT_IOCP_SW_WORKAROUND 1
@@ -32,7 +32,7 @@ static long ax45mp_iocp_sw_workaround(void)
* ANDES_SBI_EXT_IOCP_SW_WORKAROUND SBI EXT checks if the IOCP is missing and
* cache is controllable only then CMO will be applied to the platform.
*/
- ret = sbi_ecall(ANDESTECH_SBI_EXT_ANDES, ANDES_SBI_EXT_IOCP_SW_WORKAROUND,
+ ret = sbi_ecall(ANDES_SBI_EXT_ANDES, ANDES_SBI_EXT_IOCP_SW_WORKAROUND,
0, 0, 0, 0, 0, 0);
return ret.error ? 0 : ret.value;
@@ -43,7 +43,7 @@ static bool errata_probe_iocp(unsigned int stage, unsigned long arch_id, unsigne
if (!IS_ENABLED(CONFIG_ERRATA_ANDES_CMO))
return false;
- if (arch_id != ANDESTECH_AX45MP_MARCHID || impid != ANDESTECH_AX45MP_MIMPID)
+ if (arch_id != ANDES_AX45MP_MARCHID || impid != ANDES_AX45MP_MIMPID)
return false;
if (!ax45mp_iocp_sw_workaround())
diff --git a/arch/riscv/include/asm/errata_list.h b/arch/riscv/include/asm/errata_list.h
index b55b434f0059..c190393aa9db 100644
--- a/arch/riscv/include/asm/errata_list.h
+++ b/arch/riscv/include/asm/errata_list.h
@@ -12,8 +12,8 @@
#include <asm/vendorid_list.h>
#ifdef CONFIG_ERRATA_ANDES
-#define ERRATA_ANDESTECH_NO_IOCP 0
-#define ERRATA_ANDESTECH_NUMBER 1
+#define ERRATA_ANDES_NO_IOCP 0
+#define ERRATA_ANDES_NUMBER 1
#endif
#ifdef CONFIG_ERRATA_SIFIVE
diff --git a/arch/riscv/include/asm/vendorid_list.h b/arch/riscv/include/asm/vendorid_list.h
index e55407ace0c3..2f2bb0c84f9a 100644
--- a/arch/riscv/include/asm/vendorid_list.h
+++ b/arch/riscv/include/asm/vendorid_list.h
@@ -5,7 +5,7 @@
#ifndef ASM_VENDOR_LIST_H
#define ASM_VENDOR_LIST_H
-#define ANDESTECH_VENDOR_ID 0x31e
+#define ANDES_VENDOR_ID 0x31e
#define SIFIVE_VENDOR_ID 0x489
#define THEAD_VENDOR_ID 0x5b7
diff --git a/arch/riscv/kernel/alternative.c b/arch/riscv/kernel/alternative.c
index 319a1da0358b..0128b161bfda 100644
--- a/arch/riscv/kernel/alternative.c
+++ b/arch/riscv/kernel/alternative.c
@@ -43,7 +43,7 @@ static void riscv_fill_cpu_mfr_info(struct cpu_manufacturer_info_t *cpu_mfr_info
switch (cpu_mfr_info->vendor_id) {
#ifdef CONFIG_ERRATA_ANDES
- case ANDESTECH_VENDOR_ID:
+ case ANDES_VENDOR_ID:
cpu_mfr_info->patch_func = andes_errata_patch_func;
break;
#endif
--
2.34.1
On Thu, Oct 19, 2023 at 09:53:29PM +0800, Yu Chien Peter Lin wrote:
> Using "ANDES" rather than "ANDESTECH" to unify the naming
> convention with OpenSBI and U-Boot, and reduce the number
> of characters per line.
NGL, I think this is just churn and the 4-characters-per-line
saving is a weak argument & u-boot/opensbi alignment is not really
relevant. A better argument for it is probably unification with the
directory/file names, Kconfig options and with the
ANDES_SBI_EXT_OPCP_SW_WORKAROUND definitions.
/shrug,
Conor.
>
> Signed-off-by: Yu Chien Peter Lin <[email protected]>
> Reviewed-by: Charles Ci-Jyun Wu <[email protected]>
> Reviewed-by: Leo Yu-Chi Liang <[email protected]>
> ---
> Changes v1 -> v2:
> - No change
> ---
> arch/riscv/errata/andes/errata.c | 10 +++++-----
> arch/riscv/include/asm/errata_list.h | 4 ++--
> arch/riscv/include/asm/vendorid_list.h | 2 +-
> arch/riscv/kernel/alternative.c | 2 +-
> 4 files changed, 9 insertions(+), 9 deletions(-)
>
> diff --git a/arch/riscv/errata/andes/errata.c b/arch/riscv/errata/andes/errata.c
> index 197db68cc8da..d2e1abcac967 100644
> --- a/arch/riscv/errata/andes/errata.c
> +++ b/arch/riscv/errata/andes/errata.c
> @@ -18,9 +18,9 @@
> #include <asm/sbi.h>
> #include <asm/vendorid_list.h>
>
> -#define ANDESTECH_AX45MP_MARCHID 0x8000000000008a45UL
> -#define ANDESTECH_AX45MP_MIMPID 0x500UL
> -#define ANDESTECH_SBI_EXT_ANDES 0x0900031E
> +#define ANDES_AX45MP_MARCHID 0x8000000000008a45UL
> +#define ANDES_AX45MP_MIMPID 0x500UL
> +#define ANDES_SBI_EXT_ANDES 0x0900031E
>
> #define ANDES_SBI_EXT_IOCP_SW_WORKAROUND 1
>
> @@ -32,7 +32,7 @@ static long ax45mp_iocp_sw_workaround(void)
> * ANDES_SBI_EXT_IOCP_SW_WORKAROUND SBI EXT checks if the IOCP is missing and
> * cache is controllable only then CMO will be applied to the platform.
> */
> - ret = sbi_ecall(ANDESTECH_SBI_EXT_ANDES, ANDES_SBI_EXT_IOCP_SW_WORKAROUND,
> + ret = sbi_ecall(ANDES_SBI_EXT_ANDES, ANDES_SBI_EXT_IOCP_SW_WORKAROUND,
> 0, 0, 0, 0, 0, 0);
>
> return ret.error ? 0 : ret.value;
> @@ -43,7 +43,7 @@ static bool errata_probe_iocp(unsigned int stage, unsigned long arch_id, unsigne
> if (!IS_ENABLED(CONFIG_ERRATA_ANDES_CMO))
> return false;
>
> - if (arch_id != ANDESTECH_AX45MP_MARCHID || impid != ANDESTECH_AX45MP_MIMPID)
> + if (arch_id != ANDES_AX45MP_MARCHID || impid != ANDES_AX45MP_MIMPID)
> return false;
>
> if (!ax45mp_iocp_sw_workaround())
> diff --git a/arch/riscv/include/asm/errata_list.h b/arch/riscv/include/asm/errata_list.h
> index b55b434f0059..c190393aa9db 100644
> --- a/arch/riscv/include/asm/errata_list.h
> +++ b/arch/riscv/include/asm/errata_list.h
> @@ -12,8 +12,8 @@
> #include <asm/vendorid_list.h>
>
> #ifdef CONFIG_ERRATA_ANDES
> -#define ERRATA_ANDESTECH_NO_IOCP 0
> -#define ERRATA_ANDESTECH_NUMBER 1
> +#define ERRATA_ANDES_NO_IOCP 0
> +#define ERRATA_ANDES_NUMBER 1
> #endif
>
> #ifdef CONFIG_ERRATA_SIFIVE
> diff --git a/arch/riscv/include/asm/vendorid_list.h b/arch/riscv/include/asm/vendorid_list.h
> index e55407ace0c3..2f2bb0c84f9a 100644
> --- a/arch/riscv/include/asm/vendorid_list.h
> +++ b/arch/riscv/include/asm/vendorid_list.h
> @@ -5,7 +5,7 @@
> #ifndef ASM_VENDOR_LIST_H
> #define ASM_VENDOR_LIST_H
>
> -#define ANDESTECH_VENDOR_ID 0x31e
> +#define ANDES_VENDOR_ID 0x31e
> #define SIFIVE_VENDOR_ID 0x489
> #define THEAD_VENDOR_ID 0x5b7
>
> diff --git a/arch/riscv/kernel/alternative.c b/arch/riscv/kernel/alternative.c
> index 319a1da0358b..0128b161bfda 100644
> --- a/arch/riscv/kernel/alternative.c
> +++ b/arch/riscv/kernel/alternative.c
> @@ -43,7 +43,7 @@ static void riscv_fill_cpu_mfr_info(struct cpu_manufacturer_info_t *cpu_mfr_info
>
> switch (cpu_mfr_info->vendor_id) {
> #ifdef CONFIG_ERRATA_ANDES
> - case ANDESTECH_VENDOR_ID:
> + case ANDES_VENDOR_ID:
> cpu_mfr_info->patch_func = andes_errata_patch_func;
> break;
> #endif
> --
> 2.34.1
>
>
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