Depends On:
https://lore.kernel.org/lkml/[email protected]/T/
This patch series aims to enable cpufreq for IPQ5332 and IPQ9574.
For IPQ5332, a minor enhancement to Stromer Plus ops and a safe
source switch is needed before cpu freq can be enabled.
These are also included in this series. Posting this as a single
series. Please let me know if this is not correct, will split in
the subsequent revisions.
Passed the following DT related validations
make W=1 ARCH=arm64 -j16 DT_CHECKER_FLAGS='-v -m' dt_binding_check DT_SCHEMA_FILES=qcom
make W=1 ARCH=arm64 -j16 CHECK_DTBS=y DT_SCHEMA_FILES=qcom dtbs_check
For IPQ5332:
~~~~~~~~~~~
* This patch series introduces stromer plus ops which
builds on stromer ops and implements a different
set_rate and determine_rate.
A different set_rate is needed since stromer plus PLLs
do not support dynamic frequency scaling. To switch
between frequencies, we have to shut down the PLL,
configure the L and ALPHA values and turn on again. So
introduce the separate set of ops for Stromer Plus PLL.
* Update ipq_pll_stromer_plus to use clk_alpha_pll_stromer_plus_ops
instead of clk_alpha_pll_stromer_ops.
* Set 'l' value to a value that is supported on all SKUs.
* Provide safe source switch for a53pll
* Include IPQ5332 in cpufreq nvmem framework
* Add OPP details to device tree
For IPQ9574:
~~~~~~~~~~~
* Include IPQ9574 in cpufreq nvmem framework
* Add OPP details to device tree
Removed 2 patches from V1 as they have been merged
* dt-bindings: cpufreq: qcom-cpufreq-nvmem: document IPQ5332
* dt-bindings: cpufreq: qcom-cpufreq-nvmem: document IPQ9574
v4: Included a patch to fix 'kernel test robot' build error --
https://lore.kernel.org/r/[email protected]/
v5: Use devm_clk_notifier_register
Merge IPQ53xx and IPQ95xx cases with APQ8096 for speed bin selection
Add reviewed by tags
Varadarajan Narayanan (9):
clk: qcom: config IPQ_APSS_6018 should depend on QCOM_SMEM
clk: qcom: clk-alpha-pll: introduce stromer plus ops
clk: qcom: apss-ipq-pll: Use stromer plus ops for stromer plus pll
clk: qcom: apss-ipq-pll: Fix 'l' value for ipq5332_pll_config
clk: qcom: apss-ipq6018: ipq5332: add safe source switch for a53pll
cpufreq: qti: Enable cpufreq for ipq53xx
arm64: dts: qcom: ipq5332: populate the opp table based on the eFuse
cpufreq: qti: Introduce cpufreq for ipq95xx
arm64: dts: qcom: ipq9574: populate the opp table based on the eFuse
arch/arm64/boot/dts/qcom/ipq5332.dtsi | 19 +++++++++--
arch/arm64/boot/dts/qcom/ipq9574.dtsi | 21 +++++++++++-
drivers/clk/qcom/Kconfig | 1 +
drivers/clk/qcom/apss-ipq-pll.c | 4 +--
drivers/clk/qcom/apss-ipq6018.c | 58 +++++++++++++++++++++++++++++++-
drivers/clk/qcom/clk-alpha-pll.c | 63 +++++++++++++++++++++++++++++++++++
drivers/clk/qcom/clk-alpha-pll.h | 1 +
drivers/cpufreq/cpufreq-dt-platdev.c | 2 ++
drivers/cpufreq/qcom-cpufreq-nvmem.c | 12 +++++++
9 files changed, 174 insertions(+), 7 deletions(-)
--
2.7.4
The earlier 'l' value of 0x3e is for 1.5GHz. Not all SKUs support
this frequency. Hence set it to 0x2d to get 1.1GHz which is
supported in all SKUs.
The frequency can still increase above this initial configuration
made here when the cpufreq driver picks a different OPP.
Reviewed-by: Dmitry Baryshkov <[email protected]>
Reviewed-by: Konrad Dybcio <[email protected]>
Fixes: c7ef7fbb1ccf ("clk: qcom: apss-ipq-pll: add support for IPQ5332")
Signed-off-by: Kathiravan T <[email protected]>
Signed-off-by: Varadarajan Narayanan <[email protected]>
---
v4: Update commit log to indicate that cpufreq could subsequently
change the frequency based on the selected OPP
---
drivers/clk/qcom/apss-ipq-pll.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/qcom/apss-ipq-pll.c b/drivers/clk/qcom/apss-ipq-pll.c
index 18c4ffe..41279e5 100644
--- a/drivers/clk/qcom/apss-ipq-pll.c
+++ b/drivers/clk/qcom/apss-ipq-pll.c
@@ -74,7 +74,7 @@ static struct clk_alpha_pll ipq_pll_stromer_plus = {
};
static const struct alpha_pll_config ipq5332_pll_config = {
- .l = 0x3e,
+ .l = 0x2d,
.config_ctl_val = 0x4001075b,
.config_ctl_hi_val = 0x304,
.main_output_mask = BIT(0),
--
2.7.4
Stromer Plus PLL found on IPQ53xx doesn't support dynamic
frequency scaling. To achieve the same, we need to park the APPS
PLL source to GPLL0, re configure the PLL and then switch the
source to APSS_PLL_EARLY.
To support this, register a clock notifier to get the PRE_RATE
and POST_RATE notification. Change the APSS PLL source to GPLL0
when PRE_RATE notification is received, then configure the PLL
and then change back the source to APSS_PLL_EARLY.
Additionally, not all SKUs of IPQ53xx support scaling. Hence,
do the above to the SKUs that support scaling.
Reviewed-by: Dmitry Baryshkov <[email protected]>
Signed-off-by: Kathiravan T <[email protected]>
Signed-off-by: Varadarajan Narayanan <[email protected]>
---
v5: clk_notifier_register -> devm_clk_notifier_register
v3: devm_kzalloc for cpu_clk_notifier instead of global static
v2: Handle ABORT_RATE_CHANGE
Use local variable for apcs_alias0_clk_src.clkr.hw
Use single line comment instead of multi line style
---
drivers/clk/qcom/apss-ipq6018.c | 58 ++++++++++++++++++++++++++++++++++++++++-
1 file changed, 57 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/qcom/apss-ipq6018.c b/drivers/clk/qcom/apss-ipq6018.c
index 4e13a08..e6295b8 100644
--- a/drivers/clk/qcom/apss-ipq6018.c
+++ b/drivers/clk/qcom/apss-ipq6018.c
@@ -9,8 +9,11 @@
#include <linux/clk-provider.h>
#include <linux/regmap.h>
#include <linux/module.h>
+#include <linux/clk.h>
+#include <linux/soc/qcom/smem.h>
#include <dt-bindings/clock/qcom,apss-ipq.h>
+#include <dt-bindings/arm/qcom,ids.h>
#include "common.h"
#include "clk-regmap.h"
@@ -84,15 +87,68 @@ static const struct qcom_cc_desc apss_ipq6018_desc = {
.num_clks = ARRAY_SIZE(apss_ipq6018_clks),
};
+static int cpu_clk_notifier_fn(struct notifier_block *nb, unsigned long action,
+ void *data)
+{
+ struct clk_hw *hw;
+ u8 index;
+ int err;
+
+ if (action == PRE_RATE_CHANGE)
+ index = P_GPLL0;
+ else if (action == POST_RATE_CHANGE || action == ABORT_RATE_CHANGE)
+ index = P_APSS_PLL_EARLY;
+ else
+ return NOTIFY_OK;
+
+ hw = &apcs_alias0_clk_src.clkr.hw;
+ err = clk_rcg2_mux_closest_ops.set_parent(hw, index);
+
+ return notifier_from_errno(err);
+}
+
static int apss_ipq6018_probe(struct platform_device *pdev)
{
+ struct clk_hw *hw = &apcs_alias0_clk_src.clkr.hw;
+ struct notifier_block *cpu_clk_notifier;
struct regmap *regmap;
+ u32 soc_id;
+ int ret;
+
+ ret = qcom_smem_get_soc_id(&soc_id);
+ if (ret)
+ return ret;
regmap = dev_get_regmap(pdev->dev.parent, NULL);
if (!regmap)
return -ENODEV;
- return qcom_cc_really_probe(pdev, &apss_ipq6018_desc, regmap);
+ ret = qcom_cc_really_probe(pdev, &apss_ipq6018_desc, regmap);
+ if (ret)
+ return ret;
+
+ switch (soc_id) {
+ /* Only below variants of IPQ53xx support scaling */
+ case QCOM_ID_IPQ5332:
+ case QCOM_ID_IPQ5322:
+ case QCOM_ID_IPQ5300:
+ cpu_clk_notifier = devm_kzalloc(&pdev->dev,
+ sizeof(*cpu_clk_notifier),
+ GFP_KERNEL);
+ if (!cpu_clk_notifier)
+ return -ENOMEM;
+
+ cpu_clk_notifier->notifier_call = cpu_clk_notifier_fn;
+
+ ret = devm_clk_notifier_register(&pdev->dev, hw->clk, cpu_clk_notifier);
+ if (ret)
+ return ret;
+ break;
+ default:
+ break;
+ }
+
+ return 0;
}
static struct platform_driver apss_ipq6018_driver = {
--
2.7.4
IPQ95xx SoCs have different OPPs available for the CPU based on
SoC variant. This can be determined from an eFuse register
present in the silicon.
Add support to read the eFuse and populate the OPPs based on it.
Frequency 1.2GHz 1.8GHz 1.5GHz No opp-supported-hw
Limit
------------------------------------------------------------
936000000 1 1 1 1 0xf
1104000000 1 1 1 1 0xf
1200000000 1 1 1 1 0xf
1416000000 0 1 1 1 0x7
1488000000 0 1 1 1 0x7
1800000000 0 1 0 1 0x5
2208000000 0 0 0 1 0x1
-----------------------------------------------------------
Reviewed-by: Konrad Dybcio <[email protected]>
Signed-off-by: Kathiravan T <[email protected]>
Signed-off-by: Varadarajan Narayanan <[email protected]>
---
v2: cpu_speed_bin -> cpu-speed-bin in node name
Move comment to commit log
---
arch/arm64/boot/dts/qcom/ipq9574.dtsi | 21 ++++++++++++++++++++-
1 file changed, 20 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
index cc84f25..5f83ee4 100644
--- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
@@ -106,42 +106,56 @@
};
cpu_opp_table: opp-table-cpu {
- compatible = "operating-points-v2";
+ compatible = "operating-points-v2-kryo-cpu";
opp-shared;
+ nvmem-cells = <&cpu_speed_bin>;
opp-936000000 {
opp-hz = /bits/ 64 <936000000>;
opp-microvolt = <725000>;
+ opp-supported-hw = <0xf>;
clock-latency-ns = <200000>;
};
opp-1104000000 {
opp-hz = /bits/ 64 <1104000000>;
opp-microvolt = <787500>;
+ opp-supported-hw = <0xf>;
+ clock-latency-ns = <200000>;
+ };
+
+ opp-1200000000 {
+ opp-hz = /bits/ 64 <1200000000>;
+ opp-microvolt = <862500>;
+ opp-supported-hw = <0xf>;
clock-latency-ns = <200000>;
};
opp-1416000000 {
opp-hz = /bits/ 64 <1416000000>;
opp-microvolt = <862500>;
+ opp-supported-hw = <0x7>;
clock-latency-ns = <200000>;
};
opp-1488000000 {
opp-hz = /bits/ 64 <1488000000>;
opp-microvolt = <925000>;
+ opp-supported-hw = <0x7>;
clock-latency-ns = <200000>;
};
opp-1800000000 {
opp-hz = /bits/ 64 <1800000000>;
opp-microvolt = <987500>;
+ opp-supported-hw = <0x5>;
clock-latency-ns = <200000>;
};
opp-2208000000 {
opp-hz = /bits/ 64 <2208000000>;
opp-microvolt = <1062500>;
+ opp-supported-hw = <0x1>;
clock-latency-ns = <200000>;
};
};
@@ -223,6 +237,11 @@
reg = <0x000a4000 0x5a1>;
#address-cells = <1>;
#size-cells = <1>;
+
+ cpu_speed_bin: cpu-speed-bin@15 {
+ reg = <0x15 0x2>;
+ bits = <7 2>;
+ };
};
cryptobam: dma-controller@704000 {
--
2.7.4
IPQ53xx have different OPPs available for the CPU based on
SoC variant. This can be determined through use of an eFuse
register present in the silicon.
Added support for ipq53xx on nvmem driver which helps to
determine OPPs at runtime based on the eFuse register which
has the CPU frequency limits. opp-supported-hw dt binding
can be used to indicate the available OPPs for each limit.
nvmem driver also creates the "cpufreq-dt" platform_device after
passing the version matching data to the OPP framework so that the
cpufreq-dt handles the actual cpufreq implementation.
Reviewed-by: Dmitry Baryshkov <[email protected]>
Reviewed-by: Bryan O'Donoghue <[email protected]>
Signed-off-by: Kathiravan T <[email protected]>
Signed-off-by: Varadarajan Narayanan <[email protected]>
---
v5: Merge IPQ53xx with existing APQ8096 case
v2: Move IPQ53xx after APQ8096SG
---
drivers/cpufreq/cpufreq-dt-platdev.c | 1 +
drivers/cpufreq/qcom-cpufreq-nvmem.c | 6 ++++++
2 files changed, 7 insertions(+)
diff --git a/drivers/cpufreq/cpufreq-dt-platdev.c b/drivers/cpufreq/cpufreq-dt-platdev.c
index 675da7f..f43e5cd 100644
--- a/drivers/cpufreq/cpufreq-dt-platdev.c
+++ b/drivers/cpufreq/cpufreq-dt-platdev.c
@@ -180,6 +180,7 @@ static const struct of_device_id blocklist[] __initconst = {
{ .compatible = "ti,am62a7", },
{ .compatible = "ti,am62p5", },
+ { .compatible = "qcom,ipq5332", },
{ .compatible = "qcom,ipq8064", },
{ .compatible = "qcom,ipq8074", },
{ .compatible = "qcom,apq8064", },
diff --git a/drivers/cpufreq/qcom-cpufreq-nvmem.c b/drivers/cpufreq/qcom-cpufreq-nvmem.c
index 3fa1264..e7e6a6a 100644
--- a/drivers/cpufreq/qcom-cpufreq-nvmem.c
+++ b/drivers/cpufreq/qcom-cpufreq-nvmem.c
@@ -153,6 +153,11 @@ static int qcom_cpufreq_kryo_name_version(struct device *cpu_dev,
switch (msm_id) {
case QCOM_ID_MSM8996:
case QCOM_ID_APQ8096:
+ case QCOM_ID_IPQ5332:
+ case QCOM_ID_IPQ5322:
+ case QCOM_ID_IPQ5312:
+ case QCOM_ID_IPQ5302:
+ case QCOM_ID_IPQ5300:
drv->versions = 1 << (unsigned int)(*speedbin);
break;
case QCOM_ID_MSM8996SG:
@@ -406,6 +411,7 @@ static const struct of_device_id qcom_cpufreq_match_list[] __initconst = {
{ .compatible = "qcom,apq8096", .data = &match_data_kryo },
{ .compatible = "qcom,msm8996", .data = &match_data_kryo },
{ .compatible = "qcom,qcs404", .data = &match_data_qcs404 },
+ { .compatible = "qcom,ipq5332", .data = &match_data_kryo },
{ .compatible = "qcom,ipq8064", .data = &match_data_krait },
{ .compatible = "qcom,ipq8074", .data = &match_data_ipq8074 },
{ .compatible = "qcom,apq8064", .data = &match_data_krait },
--
2.7.4
IPQ53xx have different OPPs available for the CPU based on
SoC variant. This can be determined through use of an eFuse
register present in the silicon.
Add support to read the eFuse and populate the OPPs based on it.
------------------------------------------------
Frequency BIT2 BIT1 opp-supported-hw
1.1GHz 1.5GHz
------------------------------------------------
1100000000 1 1 0x7
1500000000 0 1 0x3
------------------------------------------------
Signed-off-by: Kathiravan T <[email protected]>
Signed-off-by: Varadarajan Narayanan <[email protected]>
---
v4: Change opp-supported-hw from 0xf to 0x7 in commit log
and DT entry.
v2: Fix inconsistencies in comment and move it to commit log
as suggested
Remove opp-microvolt entries as no regulator is managed by Linux
cpu_speed_bin -> cpu-speed-bin in node name
Remove "nvmem-cell-names" due to dtbs_check error
---
arch/arm64/boot/dts/qcom/ipq5332.dtsi | 19 ++++++++++++++++---
1 file changed, 16 insertions(+), 3 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/ipq5332.dtsi b/arch/arm64/boot/dts/qcom/ipq5332.dtsi
index 4206f05..42e2e48 100644
--- a/arch/arm64/boot/dts/qcom/ipq5332.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq5332.dtsi
@@ -91,11 +91,19 @@
};
cpu_opp_table: opp-table-cpu {
- compatible = "operating-points-v2";
+ compatible = "operating-points-v2-kryo-cpu";
opp-shared;
+ nvmem-cells = <&cpu_speed_bin>;
- opp-1488000000 {
- opp-hz = /bits/ 64 <1488000000>;
+ opp-1100000000 {
+ opp-hz = /bits/ 64 <1100000000>;
+ opp-supported-hw = <0x7>;
+ clock-latency-ns = <200000>;
+ };
+
+ opp-1500000000 {
+ opp-hz = /bits/ 64 <1500000000>;
+ opp-supported-hw = <0x3>;
clock-latency-ns = <200000>;
};
};
@@ -163,6 +171,11 @@
reg = <0x000a4000 0x721>;
#address-cells = <1>;
#size-cells = <1>;
+
+ cpu_speed_bin: cpu-speed-bin@1d {
+ reg = <0x1d 0x2>;
+ bits = <7 2>;
+ };
};
rng: rng@e3000 {
--
2.7.4
IPQ95xx SoCs have different OPPs available for the CPU based on
the SoC variant. This can be determined from an eFuse register
present in the silicon.
Added support for ipq95xx on nvmem driver which helps to
determine OPPs at runtime based on the eFuse register which
has the CPU frequency limits. opp-supported-hw dt binding
can be used to indicate the available OPPs for each limit.
Reviewed-by: Dmitry Baryshkov <[email protected]>
Signed-off-by: Praveenkumar I <[email protected]>
Signed-off-by: Kathiravan T <[email protected]>
Signed-off-by: Varadarajan Narayanan <[email protected]>
---
v5: Merge IPQ95xx with APQ8096 case
v2: Simplify bin selection by tweaking the order in dts
---
drivers/cpufreq/cpufreq-dt-platdev.c | 1 +
drivers/cpufreq/qcom-cpufreq-nvmem.c | 6 ++++++
2 files changed, 7 insertions(+)
diff --git a/drivers/cpufreq/cpufreq-dt-platdev.c b/drivers/cpufreq/cpufreq-dt-platdev.c
index f43e5cd..4f794ba 100644
--- a/drivers/cpufreq/cpufreq-dt-platdev.c
+++ b/drivers/cpufreq/cpufreq-dt-platdev.c
@@ -183,6 +183,7 @@ static const struct of_device_id blocklist[] __initconst = {
{ .compatible = "qcom,ipq5332", },
{ .compatible = "qcom,ipq8064", },
{ .compatible = "qcom,ipq8074", },
+ { .compatible = "qcom,ipq9574", },
{ .compatible = "qcom,apq8064", },
{ .compatible = "qcom,msm8974", },
{ .compatible = "qcom,msm8960", },
diff --git a/drivers/cpufreq/qcom-cpufreq-nvmem.c b/drivers/cpufreq/qcom-cpufreq-nvmem.c
index e7e6a6a..5827005 100644
--- a/drivers/cpufreq/qcom-cpufreq-nvmem.c
+++ b/drivers/cpufreq/qcom-cpufreq-nvmem.c
@@ -158,6 +158,11 @@ static int qcom_cpufreq_kryo_name_version(struct device *cpu_dev,
case QCOM_ID_IPQ5312:
case QCOM_ID_IPQ5302:
case QCOM_ID_IPQ5300:
+ case QCOM_ID_IPQ9514:
+ case QCOM_ID_IPQ9550:
+ case QCOM_ID_IPQ9554:
+ case QCOM_ID_IPQ9570:
+ case QCOM_ID_IPQ9574:
drv->versions = 1 << (unsigned int)(*speedbin);
break;
case QCOM_ID_MSM8996SG:
@@ -415,6 +420,7 @@ static const struct of_device_id qcom_cpufreq_match_list[] __initconst = {
{ .compatible = "qcom,ipq8064", .data = &match_data_krait },
{ .compatible = "qcom,ipq8074", .data = &match_data_ipq8074 },
{ .compatible = "qcom,apq8064", .data = &match_data_krait },
+ { .compatible = "qcom,ipq9574", .data = &match_data_kryo },
{ .compatible = "qcom,msm8974", .data = &match_data_krait },
{ .compatible = "qcom,msm8960", .data = &match_data_krait },
{},
--
2.7.4
On 20-10-23, 11:49, Varadarajan Narayanan wrote:
> Varadarajan Narayanan (9):
> cpufreq: qti: Enable cpufreq for ipq53xx
> cpufreq: qti: Introduce cpufreq for ipq95xx
Can I pick just these two ?
--
viresh
On Fri, Oct 20, 2023 at 12:39:47PM +0530, Viresh Kumar wrote:
> On 20-10-23, 11:49, Varadarajan Narayanan wrote:
> > Varadarajan Narayanan (9):
> > cpufreq: qti: Enable cpufreq for ipq53xx
> > cpufreq: qti: Introduce cpufreq for ipq95xx
>
> Can I pick just these two ?
ipq53xx patch is dependent on the previous safe source switching
patch, hence not safe to pick that.
No -> cpufreq: qti: Enable cpufreq for ipq53xx
Yes -> cpufreq: qti: Introduce cpufreq for ipq95xx
Thanks
Varada
On Fri, 20 Oct 2023 11:49:30 +0530, Varadarajan Narayanan wrote:
> Depends On:
> https://lore.kernel.org/lkml/[email protected]/T/
>
> This patch series aims to enable cpufreq for IPQ5332 and IPQ9574.
> For IPQ5332, a minor enhancement to Stromer Plus ops and a safe
> source switch is needed before cpu freq can be enabled.
>
> [...]
Applied, thanks!
[1/9] clk: qcom: config IPQ_APSS_6018 should depend on QCOM_SMEM
commit: 6a15647d0adc686226045e8046369f34d6ab03ed
[2/9] clk: qcom: clk-alpha-pll: introduce stromer plus ops
commit: 84da48921a97cee3dd1391659e93ee01d122b78b
[3/9] clk: qcom: apss-ipq-pll: Use stromer plus ops for stromer plus pll
commit: 267e29198436a8cb6770213471f72502c895096a
[4/9] clk: qcom: apss-ipq-pll: Fix 'l' value for ipq5332_pll_config
commit: 5b7a4d3d2b33398330aef69e0ff5656273483587
[5/9] clk: qcom: apss-ipq6018: ipq5332: add safe source switch for a53pll
commit: 00331227f42045314b3775957f2f7809fb3ac32f
Best regards,
--
Bjorn Andersson <[email protected]>
On 10/20/23 08:19, Varadarajan Narayanan wrote:
> Stromer Plus PLL found on IPQ53xx doesn't support dynamic
> frequency scaling. To achieve the same, we need to park the APPS
> PLL source to GPLL0, re configure the PLL and then switch the
> source to APSS_PLL_EARLY.
>
> To support this, register a clock notifier to get the PRE_RATE
> and POST_RATE notification. Change the APSS PLL source to GPLL0
> when PRE_RATE notification is received, then configure the PLL
> and then change back the source to APSS_PLL_EARLY.
>
> Additionally, not all SKUs of IPQ53xx support scaling. Hence,
> do the above to the SKUs that support scaling.
>
> Reviewed-by: Dmitry Baryshkov <[email protected]>
> Signed-off-by: Kathiravan T <[email protected]>
> Signed-off-by: Varadarajan Narayanan <[email protected]>
> ---
This looks good, however I'm not sure if registering the callback
only on SoCs that are supposed to rate-change isn't
overly-defensive. That said, I'm not particularly against it.
Acked-by: Konrad Dybcio <[email protected]>
Konrad
On Fri, 20 Oct 2023 11:49:30 +0530, Varadarajan Narayanan wrote:
> Depends On:
> https://lore.kernel.org/lkml/[email protected]/T/
>
> This patch series aims to enable cpufreq for IPQ5332 and IPQ9574.
> For IPQ5332, a minor enhancement to Stromer Plus ops and a safe
> source switch is needed before cpu freq can be enabled.
>
> [...]
Applied, thanks!
[7/9] arm64: dts: qcom: ipq5332: populate the opp table based on the eFuse
commit: 62073bc9f1ecc0d91fc260e7ae380cbadd33e9fc
[9/9] arm64: dts: qcom: ipq9574: populate the opp table based on the eFuse
commit: b36074357baf2794c825ea1c145de1d22b15380b
Best regards,
--
Bjorn Andersson <[email protected]>
Quoting Varadarajan Narayanan (2023-10-19 23:19:35)
> Stromer Plus PLL found on IPQ53xx doesn't support dynamic
> frequency scaling. To achieve the same, we need to park the APPS
> PLL source to GPLL0, re configure the PLL and then switch the
> source to APSS_PLL_EARLY.
>
> To support this, register a clock notifier to get the PRE_RATE
> and POST_RATE notification. Change the APSS PLL source to GPLL0
> when PRE_RATE notification is received, then configure the PLL
> and then change back the source to APSS_PLL_EARLY.
>
> Additionally, not all SKUs of IPQ53xx support scaling. Hence,
> do the above to the SKUs that support scaling.
>
> Reviewed-by: Dmitry Baryshkov <[email protected]>
> Signed-off-by: Kathiravan T <[email protected]>
> Signed-off-by: Varadarajan Narayanan <[email protected]>
The Kconfig change (patch#1) should be squashed into here. Otherwise
there isn't a call to qcom_smem_get_soc_id() in the clk driver.
> ---
> v5: clk_notifier_register -> devm_clk_notifier_register
> v3: devm_kzalloc for cpu_clk_notifier instead of global static
> v2: Handle ABORT_RATE_CHANGE
> Use local variable for apcs_alias0_clk_src.clkr.hw
> Use single line comment instead of multi line style
> ---
> drivers/clk/qcom/apss-ipq6018.c | 58 ++++++++++++++++++++++++++++++++++++++++-
> 1 file changed, 57 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/clk/qcom/apss-ipq6018.c b/drivers/clk/qcom/apss-ipq6018.c
> index 4e13a08..e6295b8 100644
> --- a/drivers/clk/qcom/apss-ipq6018.c
> +++ b/drivers/clk/qcom/apss-ipq6018.c
> @@ -9,8 +9,11 @@
> #include <linux/clk-provider.h>
> #include <linux/regmap.h>
> #include <linux/module.h>
> +#include <linux/clk.h>
> +#include <linux/soc/qcom/smem.h>
>
> #include <dt-bindings/clock/qcom,apss-ipq.h>
> +#include <dt-bindings/arm/qcom,ids.h>
>
> #include "common.h"
> #include "clk-regmap.h"
> @@ -84,15 +87,68 @@ static const struct qcom_cc_desc apss_ipq6018_desc = {
> .num_clks = ARRAY_SIZE(apss_ipq6018_clks),
> };
>
> +static int cpu_clk_notifier_fn(struct notifier_block *nb, unsigned long action,
> + void *data)
> +{
> + struct clk_hw *hw;
> + u8 index;
> + int err;
> +
> + if (action == PRE_RATE_CHANGE)
> + index = P_GPLL0;
> + else if (action == POST_RATE_CHANGE || action == ABORT_RATE_CHANGE)
> + index = P_APSS_PLL_EARLY;
> + else
> + return NOTIFY_OK;
> +
> + hw = &apcs_alias0_clk_src.clkr.hw;
> + err = clk_rcg2_mux_closest_ops.set_parent(hw, index);
> +
> + return notifier_from_errno(err);
> +}
> +
> static int apss_ipq6018_probe(struct platform_device *pdev)
> {
> + struct clk_hw *hw = &apcs_alias0_clk_src.clkr.hw;
> + struct notifier_block *cpu_clk_notifier;
> struct regmap *regmap;
> + u32 soc_id;
> + int ret;
> +
> + ret = qcom_smem_get_soc_id(&soc_id);
You need to explain why this information can't come from the compatible string.
> + if (ret)
> + return ret;
>
> regmap = dev_get_regmap(pdev->dev.parent, NULL);
> if (!regmap)
> return -ENODEV;
>
> - return qcom_cc_really_probe(pdev, &apss_ipq6018_desc, regmap);
> + ret = qcom_cc_really_probe(pdev, &apss_ipq6018_desc, regmap);
> + if (ret)
> + return ret;
> +
> + switch (soc_id) {
> + /* Only below variants of IPQ53xx support scaling */
> + case QCOM_ID_IPQ5332:
> + case QCOM_ID_IPQ5322:
> + case QCOM_ID_IPQ5300:
> + cpu_clk_notifier = devm_kzalloc(&pdev->dev,
> + sizeof(*cpu_clk_notifier),
> + GFP_KERNEL);
> + if (!cpu_clk_notifier)
> + return -ENOMEM;
> +
On 20-10-23, 13:33, Varadarajan Narayanan wrote:
> On Fri, Oct 20, 2023 at 12:39:47PM +0530, Viresh Kumar wrote:
> > On 20-10-23, 11:49, Varadarajan Narayanan wrote:
> > > Varadarajan Narayanan (9):
> > > cpufreq: qti: Enable cpufreq for ipq53xx
> > > cpufreq: qti: Introduce cpufreq for ipq95xx
> >
> > Can I pick just these two ?
>
> ipq53xx patch is dependent on the previous safe source switching
> patch, hence not safe to pick that.
>
> No -> cpufreq: qti: Enable cpufreq for ipq53xx
> Yes -> cpufreq: qti: Introduce cpufreq for ipq95xx
The patches don't apply cleanly. Please resend.
--
viresh
On Wed, Oct 25, 2023 at 11:55:08AM +0530, Viresh Kumar wrote:
> On 20-10-23, 13:33, Varadarajan Narayanan wrote:
> > On Fri, Oct 20, 2023 at 12:39:47PM +0530, Viresh Kumar wrote:
> > > On 20-10-23, 11:49, Varadarajan Narayanan wrote:
> > > > Varadarajan Narayanan (9):
> > > > cpufreq: qti: Enable cpufreq for ipq53xx
> > > > cpufreq: qti: Introduce cpufreq for ipq95xx
> > >
> > > Can I pick just these two ?
> >
> > ipq53xx patch is dependent on the previous safe source switching
> > patch, hence not safe to pick that.
> >
> > No -> cpufreq: qti: Enable cpufreq for ipq53xx
> > Yes -> cpufreq: qti: Introduce cpufreq for ipq95xx
>
> The patches don't apply cleanly. Please resend.
Have posted v6 with just these two patches and rebased
to latest top. Please pick that.
Thanks
Varada