On Rockchip RK3588 one of the DWC3 cores is integrated weirdly and
requires two extra clocks to be enabled. Without these extra clocks
hot-plugging USB devices is broken.
Signed-off-by: Sebastian Reichel <[email protected]>
---
drivers/usb/dwc3/core.c | 28 ++++++++++++++++++++++++++++
drivers/usb/dwc3/core.h | 4 ++++
2 files changed, 32 insertions(+)
diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
index 343d2570189f..639b768c3386 100644
--- a/drivers/usb/dwc3/core.c
+++ b/drivers/usb/dwc3/core.c
@@ -854,8 +854,20 @@ static int dwc3_clk_enable(struct dwc3 *dwc)
if (ret)
goto disable_ref_clk;
+ ret = clk_prepare_enable(dwc->utmi_clk);
+ if (ret)
+ goto disable_susp_clk;
+
+ ret = clk_prepare_enable(dwc->pipe_clk);
+ if (ret)
+ goto disable_utmi_clk;
+
return 0;
+disable_utmi_clk:
+ clk_disable_unprepare(dwc->utmi_clk);
+disable_susp_clk:
+ clk_disable_unprepare(dwc->susp_clk);
disable_ref_clk:
clk_disable_unprepare(dwc->ref_clk);
disable_bus_clk:
@@ -865,6 +877,8 @@ static int dwc3_clk_enable(struct dwc3 *dwc)
static void dwc3_clk_disable(struct dwc3 *dwc)
{
+ clk_disable_unprepare(dwc->pipe_clk);
+ clk_disable_unprepare(dwc->utmi_clk);
clk_disable_unprepare(dwc->susp_clk);
clk_disable_unprepare(dwc->ref_clk);
clk_disable_unprepare(dwc->bus_clk);
@@ -1785,6 +1799,20 @@ static int dwc3_get_clocks(struct dwc3 *dwc)
}
}
+ /* specific to Rockchip RK3588 */
+ dwc->utmi_clk = devm_clk_get_optional(dev, "utmi");
+ if (IS_ERR(dwc->utmi_clk)) {
+ return dev_err_probe(dev, PTR_ERR(dwc->utmi_clk),
+ "could not get utmi clock\n");
+ }
+
+ /* specific to Rockchip RK3588 */
+ dwc->pipe_clk = devm_clk_get_optional(dev, "pipe");
+ if (IS_ERR(dwc->pipe_clk)) {
+ return dev_err_probe(dev, PTR_ERR(dwc->pipe_clk),
+ "could not get pipe clock\n");
+ }
+
return 0;
}
diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
index a69ac67d89fe..f5e6ae6e394e 100644
--- a/drivers/usb/dwc3/core.h
+++ b/drivers/usb/dwc3/core.h
@@ -991,6 +991,8 @@ struct dwc3_scratchpad_array {
* @bus_clk: clock for accessing the registers
* @ref_clk: reference clock
* @susp_clk: clock used when the SS phy is in low power (S3) state
+ * @utmi_clk: clock used for USB2 PHY communication
+ * @pipe_clk: clock used for USB3 PHY communication
* @reset: reset control
* @regs: base address for our registers
* @regs_size: address space size
@@ -1156,6 +1158,8 @@ struct dwc3 {
struct clk *bus_clk;
struct clk *ref_clk;
struct clk *susp_clk;
+ struct clk *utmi_clk;
+ struct clk *pipe_clk;
struct reset_control *reset;
--
2.42.0
On Fri, Oct 20, 2023, Sebastian Reichel wrote:
> On Rockchip RK3588 one of the DWC3 cores is integrated weirdly and
> requires two extra clocks to be enabled. Without these extra clocks
> hot-plugging USB devices is broken.
>
> Signed-off-by: Sebastian Reichel <[email protected]>
> ---
> drivers/usb/dwc3/core.c | 28 ++++++++++++++++++++++++++++
> drivers/usb/dwc3/core.h | 4 ++++
> 2 files changed, 32 insertions(+)
>
> diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
> index 343d2570189f..639b768c3386 100644
> --- a/drivers/usb/dwc3/core.c
> +++ b/drivers/usb/dwc3/core.c
> @@ -854,8 +854,20 @@ static int dwc3_clk_enable(struct dwc3 *dwc)
> if (ret)
> goto disable_ref_clk;
>
> + ret = clk_prepare_enable(dwc->utmi_clk);
> + if (ret)
> + goto disable_susp_clk;
> +
> + ret = clk_prepare_enable(dwc->pipe_clk);
> + if (ret)
> + goto disable_utmi_clk;
> +
> return 0;
>
> +disable_utmi_clk:
> + clk_disable_unprepare(dwc->utmi_clk);
> +disable_susp_clk:
> + clk_disable_unprepare(dwc->susp_clk);
> disable_ref_clk:
> clk_disable_unprepare(dwc->ref_clk);
> disable_bus_clk:
> @@ -865,6 +877,8 @@ static int dwc3_clk_enable(struct dwc3 *dwc)
>
> static void dwc3_clk_disable(struct dwc3 *dwc)
> {
> + clk_disable_unprepare(dwc->pipe_clk);
> + clk_disable_unprepare(dwc->utmi_clk);
> clk_disable_unprepare(dwc->susp_clk);
> clk_disable_unprepare(dwc->ref_clk);
> clk_disable_unprepare(dwc->bus_clk);
> @@ -1785,6 +1799,20 @@ static int dwc3_get_clocks(struct dwc3 *dwc)
> }
> }
>
> + /* specific to Rockchip RK3588 */
> + dwc->utmi_clk = devm_clk_get_optional(dev, "utmi");
> + if (IS_ERR(dwc->utmi_clk)) {
> + return dev_err_probe(dev, PTR_ERR(dwc->utmi_clk),
> + "could not get utmi clock\n");
> + }
> +
> + /* specific to Rockchip RK3588 */
> + dwc->pipe_clk = devm_clk_get_optional(dev, "pipe");
> + if (IS_ERR(dwc->pipe_clk)) {
> + return dev_err_probe(dev, PTR_ERR(dwc->pipe_clk),
> + "could not get pipe clock\n");
> + }
> +
> return 0;
> }
>
> diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
> index a69ac67d89fe..f5e6ae6e394e 100644
> --- a/drivers/usb/dwc3/core.h
> +++ b/drivers/usb/dwc3/core.h
> @@ -991,6 +991,8 @@ struct dwc3_scratchpad_array {
> * @bus_clk: clock for accessing the registers
> * @ref_clk: reference clock
> * @susp_clk: clock used when the SS phy is in low power (S3) state
> + * @utmi_clk: clock used for USB2 PHY communication
> + * @pipe_clk: clock used for USB3 PHY communication
> * @reset: reset control
> * @regs: base address for our registers
> * @regs_size: address space size
> @@ -1156,6 +1158,8 @@ struct dwc3 {
> struct clk *bus_clk;
> struct clk *ref_clk;
> struct clk *susp_clk;
> + struct clk *utmi_clk;
> + struct clk *pipe_clk;
>
> struct reset_control *reset;
>
> --
> 2.42.0
>
Acked-by: Thinh Nguyen <[email protected]>
BR,
Thinh