This commit introduces a new config RISCV_PSEUDO_NMI to control
whether enabling the pseudo NMI feature on RISC-V.
Signed-off-by: Xu Lu <[email protected]>
---
arch/riscv/Kconfig | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index d607ab0f7c6d..487e4293f31e 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -669,6 +669,16 @@ config RISCV_BOOT_SPINWAIT
If unsure what to do here, say N.
+config RISCV_PSEUDO_NMI
+ bool "Support for NMI-like interrupts"
+ depends on !RISCV_M_MODE
+ default n
+ help
+ Adds support for mimicking Non-Maskable Interrupts through the use of
+ CSR_IE register.
+
+ If unsure, say N.
+
config ARCH_SUPPORTS_KEXEC
def_bool MMU
--
2.20.1