From: Conor Dooley <[email protected]>
A recent submission [1] from Rob has added additionalProperties: false
to the interrupt-controller child node of RISC-V cpus, highlighting that
the new cv1800b DT has been incorrectly using #address-cells.
It has no child nodes, so #address-cells is not needed. Remove it.
Link: https://patchwork.kernel.org/project/linux-riscv/patch/[email protected]/ [1]
Fixes: c3dffa879cca ("riscv: dts: sophgo: add initial CV1800B SoC device tree")
Signed-off-by: Conor Dooley <[email protected]>
---
CC: Chao Wei <[email protected]>
CC: Chen Wang <[email protected]>
CC: Rob Herring <[email protected]>
CC: Krzysztof Kozlowski <[email protected]>
CC: Paul Walmsley <[email protected]>
CC: Palmer Dabbelt <[email protected]>
CC: Albert Ou <[email protected]>
CC: [email protected]
CC: [email protected]
CC: [email protected]
---
arch/riscv/boot/dts/sophgo/cv1800b.dtsi | 1 -
1 file changed, 1 deletion(-)
diff --git a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
index df40e87ee063..aec6401a467b 100644
--- a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
+++ b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
@@ -34,7 +34,6 @@ cpu0: cpu@0 {
cpu0_intc: interrupt-controller {
compatible = "riscv,cpu-intc";
interrupt-controller;
- #address-cells = <0>;
#interrupt-cells = <1>;
};
};
--
2.39.2
On 2023/10/24 16:20, Conor Dooley wrote:
> From: Conor Dooley <[email protected]>
>
> A recent submission [1] from Rob has added additionalProperties: false
> to the interrupt-controller child node of RISC-V cpus, highlighting that
> the new cv1800b DT has been incorrectly using #address-cells.
> It has no child nodes, so #address-cells is not needed. Remove it.
>
> Link: https://patchwork.kernel.org/project/linux-riscv/patch/[email protected]/ [1]
> Fixes: c3dffa879cca ("riscv: dts: sophgo: add initial CV1800B SoC device tree")
> Signed-off-by: Conor Dooley <[email protected]>
> ---
> CC: Chao Wei <[email protected]>
> CC: Chen Wang <[email protected]>
> CC: Rob Herring <[email protected]>
> CC: Krzysztof Kozlowski <[email protected]>
> CC: Paul Walmsley <[email protected]>
> CC: Palmer Dabbelt <[email protected]>
> CC: Albert Ou <[email protected]>
> CC: [email protected]
> CC: [email protected]
> CC: [email protected]
> ---
> arch/riscv/boot/dts/sophgo/cv1800b.dtsi | 1 -
> 1 file changed, 1 deletion(-)
>
> diff --git a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
> index df40e87ee063..aec6401a467b 100644
> --- a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
> +++ b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
> @@ -34,7 +34,6 @@ cpu0: cpu@0 {
> cpu0_intc: interrupt-controller {
> compatible = "riscv,cpu-intc";
> interrupt-controller;
> - #address-cells = <0>;
> #interrupt-cells = <1>;
> };
> };
Acked-by: Chen Wang <[email protected]>
Thanks，btw, will it be merged in 6.7?
Looping Jisheng who is working on Duo/cv1800b.
On Wed, Oct 25, 2023 at 08:48:57AM +0800, Chen Wang wrote:
>
> On 2023/10/24 16:20, Conor Dooley wrote:
> > From: Conor Dooley <[email protected]>
> >
> > A recent submission [1] from Rob has added additionalProperties: false
> > to the interrupt-controller child node of RISC-V cpus, highlighting that
> > the new cv1800b DT has been incorrectly using #address-cells.
> > It has no child nodes, so #address-cells is not needed. Remove it.
> >
> > Link: https://patchwork.kernel.org/project/linux-riscv/patch/[email protected]/ [1]
> > Fixes: c3dffa879cca ("riscv: dts: sophgo: add initial CV1800B SoC device tree")
> > Signed-off-by: Conor Dooley <[email protected]>
Nice catch!
Reviewed-by: Jisheng Zhang <[email protected]>
> > ---
> > CC: Chao Wei <[email protected]>
> > CC: Chen Wang <[email protected]>
> > CC: Rob Herring <[email protected]>
> > CC: Krzysztof Kozlowski <[email protected]>
> > CC: Paul Walmsley <[email protected]>
> > CC: Palmer Dabbelt <[email protected]>
> > CC: Albert Ou <[email protected]>
> > CC: [email protected]
> > CC: [email protected]
> > CC: [email protected]
> > ---
> > arch/riscv/boot/dts/sophgo/cv1800b.dtsi | 1 -
> > 1 file changed, 1 deletion(-)
> >
> > diff --git a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
> > index df40e87ee063..aec6401a467b 100644
> > --- a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
> > +++ b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
> > @@ -34,7 +34,6 @@ cpu0: cpu@0 {
> > cpu0_intc: interrupt-controller {
> > compatible = "riscv,cpu-intc";
> > interrupt-controller;
> > - #address-cells = <0>;
> > #interrupt-cells = <1>;
> > };
> > };
>
> Acked-by: Chen Wang <[email protected]>
>
> Thanks，btw, will it be merged in 6.7?
Don't worry, this is a fix, I think Conor will submit fix PR once rc1 is out.
>
> Looping Jisheng who is working on Duo/cv1800b.
>
On Wed, Oct 25, 2023 at 11:13:39PM +0800, Jisheng Zhang wrote:
> > Thanks，btw, will it be merged in 6.7?
>
> Don't worry, this is a fix, I think Conor will submit fix PR once rc1 is out.
Yup. There's no harmful affects at runtime, it's just a fix for some
dtbs_check warnings that I noticed in linux-next. I'll send it as part
of a fixes PR at some point after -rc1.
Cheers,
Conor.
Hello:
This patch was applied to riscv/linux.git (fixes)
by Conor Dooley <[email protected]>:
On Tue, 24 Oct 2023 09:20:35 +0100 you wrote:
> From: Conor Dooley <[email protected]>
>
> A recent submission [1] from Rob has added additionalProperties: false
> to the interrupt-controller child node of RISC-V cpus, highlighting that
> the new cv1800b DT has been incorrectly using #address-cells.
> It has no child nodes, so #address-cells is not needed. Remove it.
>
> [...]
Here is the summary with links:
- [v1] riscv: dts: sophgo: remove address-cells from intc node
https://git.kernel.org/riscv/c/e80ed63affc9
You are awesome, thank you!
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