V7 Changes:
- 2/11 DT Binding: Disposed off comments from .yaml
-- added | to preserve formating.
-- removed extra spaces, restricting under 80 col.
-- replaced the "fsl,sram" property, with standard property "sram".
-- Added details about usage of sram.
-- removed the property "mu_id".
-- Added allOf:if:then: for reserved memory.
-- removed label.
- 3,4,5,6/11: DTSI changes:
-- removed the property "mu_id".
-- rename node-name & label
- 7/11 firmware: imx: add driver for NXP EdgeLock Enclave:
-- Removed dev_err for the cases of failure in memory allocation.
-- For others, coverted dev_err to dev_dbg.
-- Updated the commit msg about the details for userspace lib
V6 Changes:
- 1/11 (New): Kernel doc: "Documentation/driver-api/firmware/other_interfaces.rst" is added.
- 2/11 DT Binding: Disposed off comments from .yaml
-- replaced the "sram-pool" property, with standard property "fsl,sram".
-- removed the additional details from the description.
- 3,4,5,6/11: DTSI changes:
-- Validated using the following commands:
--- make dt_binding_check DT_SCHEMA_FILES=freescale
--- make CHECK_DTBS=y freescale/imx8ulp-evk.dtb;
make CHECK_DTBS=y freescale/imx93-11x11-evk.dtb
- 7/11 firmware: imx: add driver for NXP EdgeLock Enclave:
-- Removed:
Reported-by: kernel test robot <[email protected]>
Closes:https://lore.kernel.org/oe-kbuild-all/[email protected]
-- pr_info is removed.
-- macro "devctx_info", "devctx_dbg" & "devctx_err" is removed.
-- Updated ABI:
--- Users: user-space SE-LIB, crypto-api, imx-ocotp-ele driver , smw
--- IOCTLS: Updated the ioctl
--- read/write:
-- Correct message header validation.
--- segregated handling of the error, while msg header parsing.
-- removed TX and RX messages static allocation in state container.
-- ran coccicheck: make C=1 CHECK=scripts/coccicheck drivers/firmware/imx/*.* W=1
--- ran on all the patches.
- 8/11 firmware: imx: init-fw api exchange on imx93
-- removed TX and RX messages static allocation in state container.
-- moved the header file ele_fw_api.h, to driver/firmware/imx/
-- segregated handling of the error, while msg header parsing.
- 9/11 firmware: imx: enable trng
-- macro "devctx_info", "devctx_dbg" & "devctx_err" is removed.
-- will remove this patch, will send this patch later, including RNG and crypto-maintainers.
- 10/11 firmware: imx: enclave-fw: add handling for save/restore IMEM region
-- Linux comment style fixed.
- 10/11(old)(Removed) firmware: imx: enclave api to read-common-fuses
-- This API will be used by imx-ocotp-ele.c.
-- This patch can be sent later, when the changes to imx-ocotp-ele.c will be sent.
-- "Documentation/driver-api/firmware/other_interfaces.rst" will be update for the exported symbols:
- read_common_fuses()
- get_se_dev()
v5 Changes:
- 1/7 DT Binding: Disposed off comments from .yaml
-- to use "-", instead of "_".
-- to use generic name, concatinated with soc-id.
-- removed mu-did.
-- renamed the ele-mu to se-fw
-- moved the file from .../arm/freescale/ to .../firmware/
- 2/7 Changed the .dtsi, as per the comments.
-- removed mu-did
-- renamed the ele_mu to se-fw.
-- updated the compatible string.
-- tested the DTB.
- 4/7 Changed the .dtsi, as per the comments.
-- removed mu-did
-- renamed the ele_mu to se-fw.
-- updated the compatible string.
-- tested the DTB.
- 6/7 Changes in driver code:
-- replace pr_err with dev_err
-- removed export symbols, except one, which will be used in other driver.
-- Each API, send-recived based on device reference.
-- Divided the commits into smaller commits.
- Base Driver
-- Added ABI file.
- 7/11 (new) firmware: imx: init-fw api exchange on imx93
- 8/11 (new) firmware: imx: enable trng
- 9/11 (new) firmware: imx: enclave-fw: add handling for save/restore IMEM region
- 10/11 (new) firmware: imx: enclave api to read-common-fuses
v4 Changes:
- Post internal review, changed the name from "ele-mu" to "se-fw".
- Disposed-off comments in the dt-binding file.
- Removed the non-hw related dt-bindings from the driver code.
- Corrected the File MAINTAINERS for correct name of yaml file.
v3 Changes:
- update the commit message for documentation.
- Fixed dt-binding checking error for file- fsl,ele_mu.yaml
- Coverity fixes in the ele_mu.c
v2 Changes:
- Fixed Kernel Test Bot issues.
- Removed ".../devicetree/bindings/mailbox/fsl,muap.txt"
The NXP's i.MX EdgeLock Enclave, a HW IP creating an embedded
secure enclave within the SoC boundary to enable features like
- HSM
- SHE
- V2X
Communicates via message unit with linux kernel. This driver
is enables communication ensuring well defined message sequence
protocol between Application Core and enclave's firmware.
Driver configures multiple misc-device on the MU, for multiple
user-space applications can communicate on single MU.
It exists on some i.MX processors. e.g. i.MX8ULP, i.MX93 etc.
Pankaj Gupta (11):
Documentation/firmware: added imx/se-fw to other_interfaces
dt-bindings: arm: fsl: add imx-se-fw binding doc
arm64: dts: imx8ulp-evk: added nxp secure enclave firmware
arm64: dts: imx8ulp-evk: reserved mem-ranges to constrain ele_fw
dma-range
arm64: dts: imx93-11x11-evk: added nxp secure enclave fw
arm64: dts: imx93-11x11-evk: reserved mem-ranges
firmware: imx: add driver for NXP EdgeLock Enclave
firmware: imx: init-fw api exchange on imx93
firmware: imx: enable trng
firmware: imx: enclave-fw: add handling for save/restore IMEM region
MAINTAINERS: Added maintainer details
Documentation/ABI/testing/se-cdev | 41 +
.../bindings/firmware/fsl,imx-se-fw.yaml | 83 +
.../driver-api/firmware/other_interfaces.rst | 67 +
MAINTAINERS | 10 +
arch/arm64/boot/dts/freescale/imx8ulp-evk.dts | 15 +
arch/arm64/boot/dts/freescale/imx8ulp.dtsi | 10 +-
.../boot/dts/freescale/imx93-11x11-evk.dts | 15 +
arch/arm64/boot/dts/freescale/imx93.dtsi | 8 +-
drivers/firmware/imx/Kconfig | 21 +
drivers/firmware/imx/Makefile | 3 +
drivers/firmware/imx/ele_base_msg.c | 271 ++++
drivers/firmware/imx/ele_common.c | 294 ++++
drivers/firmware/imx/ele_common.h | 40 +
drivers/firmware/imx/ele_fw_api.c | 118 ++
drivers/firmware/imx/ele_fw_api.h | 26 +
drivers/firmware/imx/ele_trng.c | 47 +
drivers/firmware/imx/se_fw.c | 1376 +++++++++++++++++
drivers/firmware/imx/se_fw.h | 154 ++
include/linux/firmware/imx/ele_base_msg.h | 67 +
include/linux/firmware/imx/ele_mu_ioctl.h | 74 +
20 files changed, 2738 insertions(+), 2 deletions(-)
create mode 100644 Documentation/ABI/testing/se-cdev
create mode 100644 Documentation/devicetree/bindings/firmware/fsl,imx-se-fw.yaml
create mode 100644 drivers/firmware/imx/ele_base_msg.c
create mode 100644 drivers/firmware/imx/ele_common.c
create mode 100644 drivers/firmware/imx/ele_common.h
create mode 100644 drivers/firmware/imx/ele_fw_api.c
create mode 100644 drivers/firmware/imx/ele_fw_api.h
create mode 100644 drivers/firmware/imx/ele_trng.c
create mode 100644 drivers/firmware/imx/se_fw.c
create mode 100644 drivers/firmware/imx/se_fw.h
create mode 100644 include/linux/firmware/imx/ele_base_msg.h
create mode 100644 include/linux/firmware/imx/ele_mu_ioctl.h
--
2.34.1
Documented i.MX SoC's Service layer and C_DEV driver for SoC(s)
enabled with hardware IP for secure-enclaves like:
- edgelock enclave on i.MX93 & i.MX8ULP
Signed-off-by: Pankaj Gupta <[email protected]>
---
.../driver-api/firmware/other_interfaces.rst | 67 +++++++++++++++++++
1 file changed, 67 insertions(+)
diff --git a/Documentation/driver-api/firmware/other_interfaces.rst b/Documentation/driver-api/firmware/other_interfaces.rst
index 06ac89adaafb..1d21b88ef20e 100644
--- a/Documentation/driver-api/firmware/other_interfaces.rst
+++ b/Documentation/driver-api/firmware/other_interfaces.rst
@@ -49,3 +49,70 @@ of the requests on to a secure monitor (EL3).
.. kernel-doc:: drivers/firmware/stratix10-svc.c
:export:
+
+NXP i.MX Secure Enclave Enabled SoC Service layer and C_DEV driver
+------------------------------------------------------------------
+The NXP's i.MX HW IP like EdgeLock-Enclave, creating an embedded secure
+enclave within the SoC boundary to enable features like
+ - HSM
+ - SHE
+ - V2X
+
+SoC enabled with the NXP i.MX secure enclave IP(s) like EdgeLock-Enclave(ELE),
+are: i.MX93, i.MX8ULP.
+
+This driver exposes two interfaces:
+- service layer: This layer takes the two mutex locks:
+ "mu_cmd_lock" is taken to ensure one service is processed at a time. This
+ lock is not unlocked, till one service processing is complete. Multiple
+ messages can be exchanged with FW as part of one service processing.
+ "mu_lock" is taken to ensure one message is sent over MU at a time. This
+ lock is unlocked, post sending the message.
+
+- c_dev:
+ This driver configures multiple misc-devices on the MU, to exchange
+ messages from User-space application and NXP's Edgelocke Enclave firmware.
+ The driver ensures that the messages must follow the following protocol
+ defined.
+
+ Non-Secure + Secure
+ |
+ |
+ +---------+ +-------------+ |
+ | se_fw.c +<---->+imx-mailbox.c| |
+ | | | mailbox.c +<-->+------+ +------+
+ +---+-----+ +-------------+ | MU X +<-->+ ELE |
+ | +------+ +------+
+ +----------------+ |
+ | | |
+ v v |
+ logical logical |
+ receiver waiter |
+ + + |
+ | | |
+ | | |
+ | +----+------+ |
+ | | | |
+ | | | |
+ device_ctx device_ctx device_ctx |
+ |
+ User 0 User 1 User Y |
+ +------+ +------+ +------+ |
+ |misc.c| |misc.c| |misc.c| |
+ kernel space +------+ +------+ +------+ |
+ |
+ +------------------------------------------------------ |
+ | | | |
+ userspace /dev/ele_muXch0 | | |
+ /dev/ele_muXch1 | |
+ /dev/ele_muXchY |
+ |
+
+When a user sends a command to the firmware, it registers its device_ctx
+as waiter of a response from firmware.
+
+Enclave's Firmware owns the storage management, over linux filesystem.
+For this c_dev provisions a dedicated slave device called "receiver".
+
+.. kernel-doc:: drivers/firmware/imx/se_fw.c
+ :export:
--
2.34.1
Added support for NXP secure enclave called EdgeLock Enclave
firmware (se-fw) for imx8ulp-evk.
Signed-off-by: Pankaj Gupta <[email protected]>
---
arch/arm64/boot/dts/freescale/imx8ulp.dtsi | 10 +++++++++-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi
index 946f2b68d16f..7b66de3a392d 100644
--- a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi
@@ -152,7 +152,7 @@ sosc: clock-sosc {
#clock-cells = <0>;
};
- sram@2201f000 {
+ sram0: sram@2201f000 {
compatible = "mmio-sram";
reg = <0x0 0x2201f000 0x0 0x1000>;
@@ -578,4 +578,12 @@ gpiod: gpio@2e200080 {
gpio-ranges = <&iomuxc1 0 0 24>;
};
};
+
+ ele_fw2: se-fw2 {
+ compatible = "fsl,imx8ulp-se-fw";
+ mbox-names = "tx", "rx";
+ mboxes = <&s4muap 0 0>, <&s4muap 1 0>;
+ sram = <&sram0>;
+ };
+
};
--
2.34.1
Added support for NXP secure enclave called EdgeLock Enclave
firmware (se-fw) for imx93-11x11-evk.
Signed-off-by: Pankaj Gupta <[email protected]>
---
arch/arm64/boot/dts/freescale/imx93.dtsi | 8 +++++++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/freescale/imx93.dtsi b/arch/arm64/boot/dts/freescale/imx93.dtsi
index dcf6e4846ac9..197de680fd27 100644
--- a/arch/arm64/boot/dts/freescale/imx93.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx93.dtsi
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
- * Copyright 2022 NXP
+ * Copyright 2022-2023 NXP
*/
#include <dt-bindings/clock/imx93-clock.h>
@@ -925,4 +925,10 @@ ddr-pmu@4e300dc0 {
interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
};
};
+
+ ele_fw2: se-fw2 {
+ compatible = "fsl,imx93-se-fw";
+ mbox-names = "tx", "rx";
+ mboxes = <&s4muap 0 0>, <&s4muap 1 0>;
+ };
};
--
2.34.1
Some IMEM region is lost during kernel power down. Due to this,
firmware's functionaity cannot work correctly.
Saving encrypted IMEM region in kernel memory during power down,
and restore IMEM region on resume.
Signed-off-by: Gaurav Jain <[email protected]>
Signed-off-by: Pankaj Gupta <[email protected]>
---
drivers/firmware/imx/ele_base_msg.c | 53 ++++++++++
drivers/firmware/imx/ele_common.c | 115 ++++++++++++++++++++++
drivers/firmware/imx/ele_common.h | 8 ++
drivers/firmware/imx/se_fw.c | 36 +++++++
include/linux/firmware/imx/ele_base_msg.h | 14 +++
5 files changed, 226 insertions(+)
diff --git a/drivers/firmware/imx/ele_base_msg.c b/drivers/firmware/imx/ele_base_msg.c
index 3a3af2321f67..844bb0e54c02 100644
--- a/drivers/firmware/imx/ele_base_msg.c
+++ b/drivers/firmware/imx/ele_base_msg.c
@@ -216,3 +216,56 @@ int ele_start_rng(struct device *dev)
return ret;
}
+
+int ele_service_swap(struct device *dev,
+ phys_addr_t addr,
+ u32 addr_size, u16 flag)
+{
+ struct ele_mu_priv *priv = dev_get_drvdata(dev);
+ int ret;
+ unsigned int status;
+
+ ret = imx_se_alloc_tx_rx_buf(priv);
+ if (ret)
+ return ret;
+
+ ret = plat_fill_cmd_msg_hdr(priv,
+ (struct mu_hdr *)&priv->tx_msg->header,
+ ELE_SERVICE_SWAP_REQ,
+ ELE_SERVICE_SWAP_REQ_MSG_SZ,
+ true);
+ if (ret)
+ return ret;
+
+ priv->tx_msg->data[0] = flag;
+ priv->tx_msg->data[1] = addr_size;
+ priv->tx_msg->data[2] = ELE_NONE_VAL;
+ priv->tx_msg->data[3] = lower_32_bits(addr);
+ priv->tx_msg->data[4] = plat_add_msg_crc((uint32_t *)&priv->tx_msg[0],
+ ELE_SERVICE_SWAP_REQ_MSG_SZ);
+ ret = imx_ele_msg_send_rcv(priv);
+ if (ret < 0)
+ return ret;
+
+ ret = validate_rsp_hdr(priv,
+ priv->rx_msg->header,
+ ELE_SERVICE_SWAP_REQ,
+ ELE_SERVICE_SWAP_RSP_MSG_SZ,
+ true);
+ if (ret)
+ return ret;
+
+ status = RES_STATUS(priv->rx_msg->data[0]);
+ if (status != priv->success_tag) {
+ dev_err(dev, "Command Id[%d], Response Failure = 0x%x",
+ ELE_SERVICE_SWAP_REQ, status);
+ ret = -1;
+ } else {
+ if (flag == ELE_IMEM_EXPORT)
+ ret = priv->rx_msg->data[1];
+ else
+ ret = 0;
+ }
+
+ return ret;
+}
diff --git a/drivers/firmware/imx/ele_common.c b/drivers/firmware/imx/ele_common.c
index d4b829c19133..348f7194778f 100644
--- a/drivers/firmware/imx/ele_common.c
+++ b/drivers/firmware/imx/ele_common.c
@@ -45,6 +45,18 @@ void imx_se_free_tx_rx_buf(struct ele_mu_priv *priv)
devm_kfree(priv->dev, priv->rx_msg);
}
+uint32_t plat_add_msg_crc(uint32_t *msg, uint32_t msg_len)
+{
+ uint32_t i;
+ uint32_t crc = 0;
+ uint32_t nb_words = msg_len / (uint32_t)sizeof(uint32_t);
+
+ for (i = 0; i < nb_words - 1; i++)
+ crc ^= *(msg + i);
+
+ return crc;
+}
+
int imx_ele_msg_send_rcv(struct ele_mu_priv *priv)
{
unsigned int wait;
@@ -177,3 +189,106 @@ int ele_do_start_rng(struct device *dev)
return 0;
}
+
+#ifdef CONFIG_PM_SLEEP
+int save_imem(struct device *dev)
+{
+ int ret;
+ struct ele_mu_priv *priv = dev_get_drvdata(dev);
+
+ /* EXPORT command will save encrypted IMEM to given address,
+ * so later in resume, IMEM can be restored from the given
+ * address.
+ *
+ * Size must be at least 64 kB.
+ */
+ ret = ele_service_swap(dev,
+ priv->imem.phyaddr,
+ ELE_IMEM_SIZE,
+ ELE_IMEM_EXPORT);
+ if (ret < 0)
+ dev_err(dev, "Failed to export IMEM\n");
+ else
+ dev_info(dev,
+ "Exported %d bytes of encrypted IMEM\n",
+ ret);
+
+ return ret;
+}
+
+int restore_imem(struct device *dev,
+ uint8_t *pool_name)
+{
+ int ret;
+ u32 imem_state;
+ u32 *get_info_buf = NULL;
+ phys_addr_t get_info_phyaddr = 0;
+ struct ele_mu_priv *priv = dev_get_drvdata(dev);
+
+ get_info_phyaddr
+ = pool_name ? get_phy_buf_mem_pool(dev,
+ pool_name,
+ &get_info_buf,
+ DEVICE_GET_INFO_SZ)
+ : 0x0;
+
+ if (!get_info_buf) {
+ dev_err(dev, "Unable to alloc sram from sram pool\n");
+ return -ENOMEM;
+ }
+
+ ret = ele_do_start_rng(dev);
+ if (ret)
+ goto exit;
+
+ /* get info from ELE */
+ ret = ele_get_info(dev, get_info_phyaddr, ELE_GET_INFO_READ_SZ);
+ if (ret) {
+ dev_err(dev, "Failed to get info from ELE.\n");
+ goto exit;
+ }
+
+ /* Get IMEM state, if 0xFE then import IMEM */
+ imem_state = (get_info_buf[ELE_IMEM_STATE_WORD]
+ & ELE_IMEM_STATE_MASK) >> 16;
+ if (imem_state == ELE_IMEM_STATE_BAD) {
+ /* IMPORT command will restore IMEM from the given
+ * address, here size is the actual size returned by ELE
+ * during the export operation
+ */
+ ret = ele_service_swap(dev,
+ priv->imem.phyaddr,
+ priv->imem.size,
+ ELE_IMEM_IMPORT);
+ if (ret) {
+ dev_err(dev, "Failed to import IMEM\n");
+ goto exit;
+ }
+ } else
+ goto exit;
+
+ /* After importing IMEM, check if IMEM state is equal to 0xCA
+ * to ensure IMEM is fully loaded and
+ * ELE functionality can be used.
+ */
+ ret = ele_get_info(dev, get_info_phyaddr, ELE_GET_INFO_READ_SZ);
+ if (ret) {
+ dev_err(dev, "Failed to get info from ELE.\n");
+ goto exit;
+ }
+
+ imem_state = (get_info_buf[ELE_IMEM_STATE_WORD]
+ & ELE_IMEM_STATE_MASK) >> 16;
+ if (imem_state == ELE_IMEM_STATE_OK)
+ dev_info(dev, "Successfully restored IMEM\n");
+ else
+ dev_err(dev, "Failed to restore IMEM\n");
+
+exit:
+ if (pool_name && get_info_buf)
+ free_phybuf_mem_pool(dev, pool_name,
+ get_info_buf, DEVICE_GET_INFO_SZ);
+
+ return ret;
+}
+#endif
diff --git a/drivers/firmware/imx/ele_common.h b/drivers/firmware/imx/ele_common.h
index f9e1d949dc6a..e1979b555b58 100644
--- a/drivers/firmware/imx/ele_common.h
+++ b/drivers/firmware/imx/ele_common.h
@@ -9,6 +9,7 @@
#include "se_fw.h"
+uint32_t plat_add_msg_crc(uint32_t *msg, uint32_t msg_len);
int imx_ele_msg_send_rcv(struct ele_mu_priv *priv);
void imx_se_free_tx_rx_buf(struct ele_mu_priv *priv);
int imx_se_alloc_tx_rx_buf(struct ele_mu_priv *priv);
@@ -29,4 +30,11 @@ static inline int ele_trng_init(struct device *dev)
#endif
int ele_do_start_rng(struct device *dev);
+
+#ifdef CONFIG_PM_SLEEP
+int save_imem(struct device *dev);
+int restore_imem(struct device *dev,
+ uint8_t *pool_name);
#endif
+
+#endif /*__ELE_COMMON_H__ */
diff --git a/drivers/firmware/imx/se_fw.c b/drivers/firmware/imx/se_fw.c
index 3638a4fed5e7..db992b3cceb9 100644
--- a/drivers/firmware/imx/se_fw.c
+++ b/drivers/firmware/imx/se_fw.c
@@ -52,6 +52,7 @@ struct imx_info {
/* platform specific flag to enable/disable the ELE True RNG */
bool start_rng;
bool enable_ele_trng;
+ bool imem_mgmt;
};
struct imx_info_list {
@@ -82,6 +83,7 @@ static const struct imx_info_list imx8ulp_info = {
.init_fw = false,
.start_rng = true,
.enable_ele_trng = false,
+ .imem_mgmt = true,
},
},
};
@@ -107,6 +109,7 @@ static const struct imx_info_list imx93_info = {
.init_fw = true,
.start_rng = true,
.enable_ele_trng = true,
+ .imem_mgmt = false,
},
},
};
@@ -1062,6 +1065,17 @@ static int se_probe_cleanup(struct platform_device *pdev)
if (priv->rx_chan)
mbox_free_channel(priv->rx_chan);
+ /* free the buffer in ele-mu remove, previously allocated
+ * in ele-mu probe to store encrypted IMEM
+ */
+ if (priv->imem.buf) {
+ dmam_free_coherent(&pdev->dev,
+ ELE_IMEM_SIZE,
+ priv->imem.buf,
+ priv->imem.phyaddr);
+ priv->imem.buf = NULL;
+ }
+
if (priv->flags & RESERVED_DMA_POOL) {
of_reserved_mem_device_release(dev);
priv->flags &= (~RESERVED_DMA_POOL);
@@ -1281,6 +1295,18 @@ static int se_fw_probe(struct platform_device *pdev)
dev_err(dev, "Failed to init ele-trng\n");
}
+ if (info->imem_mgmt) {
+ /* allocate buffer where ELE store encrypted IMEM */
+ priv->imem.buf = dmam_alloc_coherent(dev, ELE_IMEM_SIZE,
+ &priv->imem.phyaddr,
+ GFP_KERNEL);
+ if (!priv->imem.buf) {
+ dev_err(dev,
+ "dmam-alloc-failed: To store encr-IMEM.\n");
+ ret = -ENOMEM;
+ goto exit;
+ }
+ }
dev_info(dev, "i.MX secure-enclave: %s interface to firmware, configured.\n",
info->pdev_name[1]);
@@ -1303,17 +1329,27 @@ static int se_fw_remove(struct platform_device *pdev)
#ifdef CONFIG_PM_SLEEP
static int se_fw_suspend(struct device *dev)
{
+ struct ele_mu_priv *priv = dev_get_drvdata(dev);
+ const struct imx_info *info = priv->info;
+
+ if (info && info->imem_mgmt)
+ priv->imem.size = save_imem(dev);
+
return 0;
}
static int se_fw_resume(struct device *dev)
{
struct ele_mu_priv *priv = dev_get_drvdata(dev);
+ const struct imx_info *info = priv->info;
int i;
for (i = 0; i < priv->max_dev_ctx; i++)
wake_up_interruptible(&priv->ctxs[i]->wq);
+ if (info && info->imem_mgmt)
+ restore_imem(dev, info->pool_name);
+
return 0;
}
#endif
diff --git a/include/linux/firmware/imx/ele_base_msg.h b/include/linux/firmware/imx/ele_base_msg.h
index 3ca4b47e4c4e..f027f687de2e 100644
--- a/include/linux/firmware/imx/ele_base_msg.h
+++ b/include/linux/firmware/imx/ele_base_msg.h
@@ -45,9 +45,23 @@
#define ELE_GET_TRNG_STATE_RETRY_COUNT 0x5
#define CSAL_TRNG_STATE_MASK 0x0000ffff
+#define ELE_SERVICE_SWAP_REQ 0xDF
+#define ELE_SERVICE_SWAP_REQ_MSG_SZ 0x18
+#define ELE_SERVICE_SWAP_RSP_MSG_SZ 0x0C
+#define ELE_IMEM_SIZE 0x10000
+#define ELE_IMEM_STATE_OK 0xCA
+#define ELE_IMEM_STATE_BAD 0xFE
+#define ELE_IMEM_STATE_WORD 0x27
+#define ELE_IMEM_STATE_MASK 0x00ff0000
+#define ELE_IMEM_EXPORT 0x1
+#define ELE_IMEM_IMPORT 0x2
+
int ele_get_info(struct device *dev, phys_addr_t addr, u32 data_size);
int ele_ping(struct device *dev);
int ele_start_rng(struct device *dev);
int ele_get_trng_state(struct device *dev);
+int ele_service_swap(struct device *dev,
+ phys_addr_t addr,
+ u32 addr_size, u16 flag);
#endif
--
2.34.1
EdgeLock Enclave are has a hardware limitation of restricted access
to the DDR memory range:
- 0x80000000 0x9FFFFFFF
ELE-MU driver requireis 1MB of memory. In this patch, reserving
1MB of ddr memory region from the lower 32-bit range.
Signed-off-by: Dong Aisheng <[email protected]>
Signed-off-by: Pankaj Gupta <[email protected]>
---
arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts b/arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts
index cafd39130eb8..bcb4ae931c64 100644
--- a/arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts
@@ -7,6 +7,10 @@
#include "imx93.dtsi"
+&ele_fw2 {
+ memory-region = <&ele_reserved>;
+};
+
/ {
model = "NXP i.MX93 11X11 EVK board";
compatible = "fsl,imx93-11x11-evk", "fsl,imx93";
@@ -68,6 +72,17 @@ reg_vref_1v8: regulator-adc-vref {
regulator-max-microvolt = <1800000>;
};
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ ele_reserved: ele-reserved@a4120000 {
+ compatible = "shared-dma-pool";
+ reg = <0 0xa4120000 0 0x100000>;
+ no-map;
+ };
+ };
+
reg_usdhc2_vmmc: regulator-usdhc2 {
compatible = "regulator-fixed";
pinctrl-names = "default";
--
2.34.1
On imx93 platforms, exchange init-fw message with enclave's firmware
is to be done.
Signed-off-by: Pankaj Gupta <[email protected]>
---
drivers/firmware/imx/Makefile | 2 +-
drivers/firmware/imx/ele_fw_api.c | 51 +++++++++++++++++++++++++++++++
drivers/firmware/imx/ele_fw_api.h | 20 ++++++++++++
drivers/firmware/imx/se_fw.c | 13 +++++++-
4 files changed, 84 insertions(+), 2 deletions(-)
create mode 100644 drivers/firmware/imx/ele_fw_api.c
create mode 100644 drivers/firmware/imx/ele_fw_api.h
diff --git a/drivers/firmware/imx/Makefile b/drivers/firmware/imx/Makefile
index 77ec0f922788..d61f06a8050a 100644
--- a/drivers/firmware/imx/Makefile
+++ b/drivers/firmware/imx/Makefile
@@ -1,5 +1,5 @@
# SPDX-License-Identifier: GPL-2.0
obj-$(CONFIG_IMX_DSP) += imx-dsp.o
obj-$(CONFIG_IMX_SCU) += imx-scu.o misc.o imx-scu-irq.o rm.o imx-scu-soc.o
-sec_enclave-objs = se_fw.o ele_common.o ele_base_msg.o
+sec_enclave-objs = se_fw.o ele_common.o ele_base_msg.o ele_fw_api.o
obj-${CONFIG_IMX_SEC_ENCLAVE} += sec_enclave.o
diff --git a/drivers/firmware/imx/ele_fw_api.c b/drivers/firmware/imx/ele_fw_api.c
new file mode 100644
index 000000000000..55dda9d6531a
--- /dev/null
+++ b/drivers/firmware/imx/ele_fw_api.c
@@ -0,0 +1,51 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright 2023 NXP
+ */
+
+#include <linux/dma-mapping.h>
+
+#include "ele_common.h"
+#include "ele_fw_api.h"
+
+int ele_init_fw(struct device *dev)
+{
+ struct ele_mu_priv *priv = dev_get_drvdata(dev);
+ unsigned int status;
+ int ret;
+
+ ret = imx_se_alloc_tx_rx_buf(priv);
+ if (ret)
+ return ret;
+
+ ret = plat_fill_cmd_msg_hdr(priv,
+ (struct mu_hdr *)&priv->tx_msg->header,
+ ELE_INIT_FW_REQ, ELE_INIT_FW_REQ_SZ,
+ false);
+ if (ret)
+ goto exit;
+
+ ret = imx_ele_msg_send_rcv(priv);
+ if (ret < 0)
+ goto exit;
+
+ ret = validate_rsp_hdr(priv,
+ priv->rx_msg->header,
+ ELE_INIT_FW_REQ,
+ ELE_INIT_FW_RSP_SZ,
+ false);
+ if (ret)
+ goto exit;
+
+ status = RES_STATUS(priv->rx_msg->data[0]);
+ if (status != priv->success_tag) {
+ dev_err(dev, "Command Id[%d], Response Failure = 0x%x",
+ ELE_INIT_FW_REQ, status);
+ ret = -1;
+ }
+
+exit:
+ imx_se_free_tx_rx_buf(priv);
+
+ return ret;
+}
diff --git a/drivers/firmware/imx/ele_fw_api.h b/drivers/firmware/imx/ele_fw_api.h
new file mode 100644
index 000000000000..21bb35b4041f
--- /dev/null
+++ b/drivers/firmware/imx/ele_fw_api.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2023 NXP
+ */
+
+#ifndef ELE_FW_API_H
+#define ELE_FW_API_H
+
+#include <linux/hw_random.h>
+
+#define MESSAGING_VERSION_7 0x7
+
+#define ELE_INIT_FW_REQ 0x17
+#define ELE_INIT_FW_REQ_SZ 0x04
+#define ELE_INIT_FW_RSP_SZ 0x08
+
+
+int ele_init_fw(struct device *dev);
+
+#endif /* ELE_FW_API_H */
diff --git a/drivers/firmware/imx/se_fw.c b/drivers/firmware/imx/se_fw.c
index fc06e9076d00..92dc8ea58960 100644
--- a/drivers/firmware/imx/se_fw.c
+++ b/drivers/firmware/imx/se_fw.c
@@ -24,6 +24,7 @@
#include <linux/sys_soc.h>
#include "se_fw.h"
+#include "ele_fw_api.h"
#define SOC_ID_OF_IMX8ULP 0x084D
#define SOC_ID_OF_IMX93 0x9300
@@ -46,6 +47,7 @@ struct imx_info {
uint8_t *mbox_rx_name;
uint8_t *pool_name;
bool reserved_dma_ranges;
+ bool init_fw;
};
struct imx_info_list {
@@ -73,6 +75,7 @@ static const struct imx_info_list imx8ulp_info = {
.mbox_rx_name = "rx",
.pool_name = "sram",
.reserved_dma_ranges = true,
+ .init_fw = false,
},
},
};
@@ -95,8 +98,9 @@ static const struct imx_info_list imx93_info = {
.mbox_rx_name = "rx",
.pool_name = NULL,
.reserved_dma_ranges = true,
+ .init_fw = true,
},
- },
+ },
};
static const struct of_device_id se_fw_match[] = {
@@ -1236,6 +1240,13 @@ static int se_fw_probe(struct platform_device *pdev)
priv->flags |= RESERVED_DMA_POOL;
}
+ if (info->init_fw) {
+ /* start initializing ele fw */
+ ret = ele_init_fw(dev);
+ if (ret)
+ dev_err(dev, "Failed to initialize ele fw.\n");
+ }
+
if (info->socdev) {
ret = imx_soc_device_register(dev, info);
if (ret) {
--
2.34.1
EdgeLock Enclave are has a hardware limitation of restricted access
to the DDR memory range:
- 0x90000000 - 0xAFFFFFFF
ELE-FW driver requireis 1MB of memory. In this patch the we are reserving
1MB of ddr memory region from the lower 32-bit range.
Signed-off-by: Dong Aisheng <[email protected]>
Signed-off-by: Pankaj Gupta <[email protected]>
---
arch/arm64/boot/dts/freescale/imx8ulp-evk.dts | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts b/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts
index 69dd8e31027c..d5cdce62a760 100644
--- a/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts
@@ -19,6 +19,17 @@ memory@80000000 {
device_type = "memory";
reg = <0x0 0x80000000 0 0x80000000>;
};
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ ele_reserved: ele-reserved@90000000 {
+ compatible = "shared-dma-pool";
+ reg = <0 0x90000000 0 0x100000>;
+ no-map;
+ };
+ };
reserved-memory {
#address-cells = <2>;
@@ -146,6 +157,10 @@ &usdhc0 {
status = "okay";
};
+&ele_fw2 {
+ memory-region = <&ele_reserved>;
+};
+
&fec {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&pinctrl_enet>;
--
2.34.1
MAINTAINERS: Added maintainer details for se-fw driver.
Signed-off-by: Pankaj Gupta <[email protected]>
---
MAINTAINERS | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index dd5de540ec0b..984751d7514a 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -13758,6 +13758,16 @@ F: mm/
F: tools/mm/
F: tools/testing/selftests/mm/
+NXP EDGELOCK(SECURE) ENCLAVE FIRMWARE DRIVER
+M: Pankaj Gupta <[email protected]>
+R: NXP Linux Team <[email protected]>
+L: [email protected]
+S: Maintained
+F: Documentation/devicetree/bindings/arm/freescale/fsl,se-fw.yaml
+F: drivers/firmware/imx/ele*.*
+F: drivers/firmware/imx/se*.*
+F: include/linux/firmware/imx/ele*.*
+
MEMORY TECHNOLOGY DEVICES (MTD)
M: Miquel Raynal <[email protected]>
M: Richard Weinberger <[email protected]>
--
2.34.1
The NXP's i.MX EdgeLock Enclave, a HW IP creating an embedded
secure enclave within the SoC boundary to enable features like
- HSM
- SHE
- V2X
Communicates via message unit with linux kernel. This driver
is enables communication ensuring well defined message sequence
protocol between Application Core and enclave's firmware.
Driver configures multiple misc-device on the MU, for multiple
user-space applications can communicate on single MU.
It exists on some i.MX processors. e.g. i.MX8ULP, i.MX93 etc.
Signed-off-by: Pankaj Gupta <[email protected]>
---
.../bindings/firmware/fsl,imx-se-fw.yaml | 83 +++++++++++++++++++
1 file changed, 83 insertions(+)
create mode 100644 Documentation/devicetree/bindings/firmware/fsl,imx-se-fw.yaml
diff --git a/Documentation/devicetree/bindings/firmware/fsl,imx-se-fw.yaml b/Documentation/devicetree/bindings/firmware/fsl,imx-se-fw.yaml
new file mode 100644
index 000000000000..0503ea497d61
--- /dev/null
+++ b/Documentation/devicetree/bindings/firmware/fsl,imx-se-fw.yaml
@@ -0,0 +1,83 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/firmware/fsl,imx-se-fw.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NXP i.MX EdgeLock Enclave Firmware (ELEFW)
+
+maintainers:
+ - Pankaj Gupta <[email protected]>
+
+description:
+ The NXP's i.MX EdgeLock Enclave, a HW IP creating an embedded
+ secure enclave within the SoC boundary to enable features like
+ - HSM
+ - SHE
+ - V2X
+
+ It uses message unit to communicate and coordinate to pass messages
+ (e.g., data, status and control) through its interfaces.
+
+properties:
+ compatible:
+ enum:
+ - fsl,imx8ulp-se-fw
+ - fsl,imx93-se-fw
+
+ mboxes:
+ description:
+ All MU channels must be within the same MU instance. Cross instances are
+ not allowed. Users need to ensure that used MU instance does not conflict
+ with other execution environments.
+ items:
+ - description: TX0 MU channel
+ - description: RX0 MU channel
+
+ mbox-names:
+ items:
+ - const: tx
+ - const: rx
+
+ memory-region:
+ items:
+ - description: Reserved memory region that can be accessed by firmware. Used for
+ exchanging the buffers between driver and firmware.
+
+ sram:
+ description: Phandle to the device SRAM
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+
+required:
+ - compatible
+ - mboxes
+ - mbox-names
+
+allOf:
+ # memory-region
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - fsl,imx8ulp-se-fw
+ - fsl,imx93-se-fw
+ then:
+ required:
+ - memory-region
+ else:
+ not:
+ required:
+ - memory-region
+
+additionalProperties: false
+
+examples:
+ - |
+ se-fw2 {
+ compatible = "fsl,imx8ulp-se-fw";
+ mbox-names = "tx", "rx";
+ mboxes = <&s4muap 0 0>, <&s4muap 1 0>;
+ };
+
+...
--
2.34.1
The Edgelock Enclave , is the secure enclave embedded in the SoC
to support the features like HSM, SHE & V2X, using message based
communication channel.
ELE FW communicates on a dedicated MU with application core where
kernel is running. It exists on specific i.MX processors. e.g.
i.MX8ULP, i.MX93.
User-space library using this driver:
- i.MX Secure Enclave library:
-- URL: https://github.com/nxp-imx/imx-secure-enclave.git,
- i.MX Secure Middle-Ware:
-- URL: https://github.com/nxp-imx/imx-smw.git
Signed-off-by: Pankaj Gupta <[email protected]>
---
Documentation/ABI/testing/se-cdev | 41 +
drivers/firmware/imx/Kconfig | 12 +
drivers/firmware/imx/Makefile | 2 +
drivers/firmware/imx/ele_base_msg.c | 101 ++
drivers/firmware/imx/ele_common.c | 139 +++
drivers/firmware/imx/ele_common.h | 30 +
drivers/firmware/imx/se_fw.c | 1308 +++++++++++++++++++++
drivers/firmware/imx/se_fw.h | 154 +++
include/linux/firmware/imx/ele_base_msg.h | 40 +
include/linux/firmware/imx/ele_mu_ioctl.h | 74 ++
10 files changed, 1901 insertions(+)
create mode 100644 Documentation/ABI/testing/se-cdev
create mode 100644 drivers/firmware/imx/ele_base_msg.c
create mode 100644 drivers/firmware/imx/ele_common.c
create mode 100644 drivers/firmware/imx/ele_common.h
create mode 100644 drivers/firmware/imx/se_fw.c
create mode 100644 drivers/firmware/imx/se_fw.h
create mode 100644 include/linux/firmware/imx/ele_base_msg.h
create mode 100644 include/linux/firmware/imx/ele_mu_ioctl.h
diff --git a/Documentation/ABI/testing/se-cdev b/Documentation/ABI/testing/se-cdev
new file mode 100644
index 000000000000..14a7143fcaf3
--- /dev/null
+++ b/Documentation/ABI/testing/se-cdev
@@ -0,0 +1,41 @@
+What: /dev/<se>_mu[0-9]+_ch[0-9]+
+Date: August 2023
+KernelVersion: 6.6
+Contact: [email protected], [email protected]
+Description:
+ NXP offers multiple hardware IP(s) for secure-enclaves like EdgeLock-
+ Enclave(ELE), SECO. The character device file-descriptors
+ /dev/<se>_mu*_ch* are the interface between user-space NXP's secure-
+ enclave shared-library and the kernel driver.
+
+ The ioctl(2)-based ABI is defined and documented in
+ [include]<linux/firmware/imx/ele_mu_ioctl.h>
+ ioctl(s) are used primarily for:
+ - shared memory management
+ - allocation of I/O buffers
+ - get mu info
+ - setting a dev-ctx as receiver that is slave to fw
+
+ The following file operations are supported:
+
+ open(2)
+ Currently the only useful flags are O_RDWR.
+
+ read(2)
+ Every read() from the opened character device context is waiting on
+ wakeup_intruptible, that gets set by the registered mailbox callback
+ function; indicating a message received from the firmware on message-
+ unit.
+
+ write(2)
+ Every write() to the opened character device context needs to acquire
+ mailbox_lock, before sending message on to the message unit.
+
+ close(2)
+ Stops and free up the I/O contexts that was associated
+ with the file descriptor.
+
+Users: https://github.com/nxp-imx/imx-secure-enclave.git,
+ https://github.com/nxp-imx/imx-smw.git
+ crypto/skcipher,
+ drivers/nvmem/imx-ocotp-ele.c
diff --git a/drivers/firmware/imx/Kconfig b/drivers/firmware/imx/Kconfig
index c027d99f2a59..2822e5d4b24c 100644
--- a/drivers/firmware/imx/Kconfig
+++ b/drivers/firmware/imx/Kconfig
@@ -28,3 +28,15 @@ config IMX_SCU_PD
depends on IMX_SCU
help
The System Controller Firmware (SCFW) based power domain driver.
+
+config IMX_SEC_ENCLAVE
+ tristate "i.MX Embedded Secure Enclave - EdgeLock Enclave Firmware driver."
+ depends on IMX_MBOX && ARCH_MXC && ARM64
+ default m if ARCH_MXC
+
+ help
+ It is possible to use APIs exposed by the iMX Secure Enclave HW IP called:
+ - EdgeLock Enclave Firmware (for i.MX8ULP, i.MX93),
+ like base, HSM, V2X & SHE using the SAB protocol via the shared Messaging
+ Unit. This driver exposes these interfaces via a set of file descriptors
+ allowing to configure shared memory, send and receive messages.
diff --git a/drivers/firmware/imx/Makefile b/drivers/firmware/imx/Makefile
index 8f9f04a513a8..77ec0f922788 100644
--- a/drivers/firmware/imx/Makefile
+++ b/drivers/firmware/imx/Makefile
@@ -1,3 +1,5 @@
# SPDX-License-Identifier: GPL-2.0
obj-$(CONFIG_IMX_DSP) += imx-dsp.o
obj-$(CONFIG_IMX_SCU) += imx-scu.o misc.o imx-scu-irq.o rm.o imx-scu-soc.o
+sec_enclave-objs = se_fw.o ele_common.o ele_base_msg.o
+obj-${CONFIG_IMX_SEC_ENCLAVE} += sec_enclave.o
diff --git a/drivers/firmware/imx/ele_base_msg.c b/drivers/firmware/imx/ele_base_msg.c
new file mode 100644
index 000000000000..813f769f7bc3
--- /dev/null
+++ b/drivers/firmware/imx/ele_base_msg.c
@@ -0,0 +1,101 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2021-2023 NXP
+ */
+
+#include <linux/types.h>
+#include <linux/completion.h>
+
+#include <linux/firmware/imx/ele_base_msg.h>
+#include <linux/firmware/imx/ele_mu_ioctl.h>
+
+#include "ele_common.h"
+
+int ele_get_info(struct device *dev, phys_addr_t addr, u32 data_size)
+{
+ struct ele_mu_priv *priv = dev_get_drvdata(dev);
+ int ret;
+ unsigned int status;
+
+ ret = imx_se_alloc_tx_rx_buf(priv);
+ if (ret)
+ return ret;
+
+ ret = plat_fill_cmd_msg_hdr(priv,
+ (struct mu_hdr *)&priv->tx_msg->header,
+ ELE_GET_INFO_REQ,
+ ELE_GET_INFO_REQ_MSG_SZ,
+ true);
+ if (ret)
+ goto exit;
+
+ priv->tx_msg->data[0] = upper_32_bits(addr);
+ priv->tx_msg->data[1] = lower_32_bits(addr);
+ priv->tx_msg->data[2] = data_size;
+ ret = imx_ele_msg_send_rcv(priv);
+ if (ret < 0)
+ goto exit;
+
+ ret = validate_rsp_hdr(priv,
+ priv->rx_msg->header,
+ ELE_GET_INFO_REQ,
+ ELE_GET_INFO_RSP_MSG_SZ,
+ true);
+ if (ret)
+ goto exit;
+
+ status = RES_STATUS(priv->rx_msg->data[0]);
+ if (status != priv->success_tag) {
+ dev_err(dev, "Command Id[%d], Response Failure = 0x%x",
+ ELE_GET_INFO_REQ, status);
+ ret = -1;
+ }
+
+exit:
+ imx_se_free_tx_rx_buf(priv);
+
+ return ret;
+}
+
+int ele_ping(struct device *dev)
+{
+ struct ele_mu_priv *priv = dev_get_drvdata(dev);
+ int ret;
+ unsigned int status;
+
+ ret = imx_se_alloc_tx_rx_buf(priv);
+ if (ret)
+ return ret;
+
+ ret = plat_fill_cmd_msg_hdr(priv,
+ (struct mu_hdr *)&priv->tx_msg->header,
+ ELE_PING_REQ, ELE_PING_REQ_SZ,
+ true);
+ if (ret) {
+ pr_err("Error: plat_fill_cmd_msg_hdr failed.\n");
+ goto exit;
+ }
+
+ ret = imx_ele_msg_send_rcv(priv);
+ if (ret)
+ goto exit;
+
+ ret = validate_rsp_hdr(priv,
+ priv->rx_msg->header,
+ ELE_PING_REQ,
+ ELE_PING_RSP_SZ,
+ true);
+ if (ret)
+ goto exit;
+
+ status = RES_STATUS(priv->rx_msg->data[0]);
+ if (status != priv->success_tag) {
+ dev_err(dev, "Command Id[%d], Response Failure = 0x%x",
+ ELE_PING_REQ, status);
+ ret = -1;
+ }
+exit:
+ imx_se_free_tx_rx_buf(priv);
+
+ return ret;
+}
diff --git a/drivers/firmware/imx/ele_common.c b/drivers/firmware/imx/ele_common.c
new file mode 100644
index 000000000000..4410245a19ec
--- /dev/null
+++ b/drivers/firmware/imx/ele_common.c
@@ -0,0 +1,139 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2023 NXP
+ */
+
+#include "ele_common.h"
+#include "se_fw.h"
+
+int imx_se_alloc_tx_rx_buf(struct ele_mu_priv *priv)
+{
+ int ret = 0;
+
+ priv->tx_msg = devm_kzalloc(priv->dev,
+ sizeof(*priv->tx_msg),
+ GFP_KERNEL);
+ if (!priv->tx_msg) {
+ ret = -ENOMEM;
+ dev_err(priv->dev, "Fail allocate mem for tx_msg.\n");
+ return ret;
+ }
+
+ priv->rx_msg = devm_kzalloc(priv->dev,
+ sizeof(*priv->rx_msg),
+ GFP_KERNEL);
+
+ if (!priv->rx_msg) {
+ ret = -ENOMEM;
+ dev_err(priv->dev, "Fail allocate mem for rx_msg.\n");
+ return ret;
+ }
+
+ return ret;
+}
+
+void imx_se_free_tx_rx_buf(struct ele_mu_priv *priv)
+{
+ if (priv->tx_msg)
+ devm_kfree(priv->dev, priv->tx_msg);
+
+ if (priv->rx_msg)
+ devm_kfree(priv->dev, priv->rx_msg);
+}
+
+int imx_ele_msg_send_rcv(struct ele_mu_priv *priv)
+{
+ unsigned int wait;
+ int err;
+
+ mutex_lock(&priv->mu_cmd_lock);
+ mutex_lock(&priv->mu_lock);
+
+ err = mbox_send_message(priv->tx_chan, priv->tx_msg);
+ if (err < 0) {
+ pr_err("Error: mbox_send_message failure.\n");
+ mutex_unlock(&priv->mu_lock);
+ mutex_unlock(&priv->mu_cmd_lock);
+ return err;
+ }
+ err = 0;
+
+ mutex_unlock(&priv->mu_lock);
+
+ wait = msecs_to_jiffies(1000);
+ if (!wait_for_completion_timeout(&priv->done, wait)) {
+ pr_err("Error: wait_for_completion timed out.\n");
+ err = -ETIMEDOUT;
+ }
+
+ mutex_unlock(&priv->mu_cmd_lock);
+
+ return err;
+}
+
+/* Fill a command message header with a given command ID and length in bytes. */
+int plat_fill_cmd_msg_hdr(struct ele_mu_priv *priv,
+ struct mu_hdr *hdr,
+ uint8_t cmd,
+ uint32_t len,
+ bool is_base_api)
+{
+ hdr->tag = priv->cmd_tag;
+ hdr->ver = (is_base_api) ? priv->base_api_ver : priv->fw_api_ver;
+ hdr->command = cmd;
+ hdr->size = len >> 2;
+
+ return 0;
+}
+
+int validate_rsp_hdr(struct ele_mu_priv *priv, unsigned int header,
+ uint8_t msg_id, uint8_t sz, bool is_base_api)
+{
+ unsigned int tag, command, size, ver;
+ int ret = -EINVAL;
+
+ tag = MSG_TAG(header);
+ command = MSG_COMMAND(header);
+ size = MSG_SIZE(header);
+ ver = MSG_VER(header);
+
+ do {
+ if (tag != priv->rsp_tag) {
+ dev_err(priv->dev,
+ "MSG[0x%x] Hdr: Resp tag mismatch. (0x%x != 0x%x)",
+ msg_id, tag, priv->rsp_tag);
+ break;
+ }
+
+ if (command != msg_id) {
+ dev_err(priv->dev,
+ "MSG Header: Cmd id mismatch. (0x%x != 0x%x)",
+ command, msg_id);
+ break;
+ }
+
+ if (size != (sz >> 2)) {
+ dev_err(priv->dev,
+ "MSG[0x%x] Hdr: Cmd size mismatch. (0x%x != 0x%x)",
+ msg_id, size, (sz >> 2));
+ break;
+ }
+
+ if (is_base_api && (ver != priv->base_api_ver)) {
+ dev_err(priv->dev,
+ "MSG[0x%x] Hdr: Base API Vers mismatch. (0x%x != 0x%x)",
+ msg_id, ver, priv->base_api_ver);
+ break;
+ } else if (!is_base_api && ver != priv->fw_api_ver) {
+ dev_err(priv->dev,
+ "MSG[0x%x] Hdr: FW API Vers mismatch. (0x%x != 0x%x)",
+ msg_id, ver, priv->fw_api_ver);
+ break;
+ }
+
+ ret = 0;
+
+ } while (false);
+
+ return ret;
+}
diff --git a/drivers/firmware/imx/ele_common.h b/drivers/firmware/imx/ele_common.h
new file mode 100644
index 000000000000..284b7f66d8e3
--- /dev/null
+++ b/drivers/firmware/imx/ele_common.h
@@ -0,0 +1,30 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2023 NXP
+ */
+
+
+#ifndef __ELE_COMMON_H__
+#define __ELE_COMMON_H__
+
+#include "se_fw.h"
+
+int imx_ele_msg_send_rcv(struct ele_mu_priv *priv);
+void imx_se_free_tx_rx_buf(struct ele_mu_priv *priv);
+int imx_se_alloc_tx_rx_buf(struct ele_mu_priv *priv);
+int validate_rsp_hdr(struct ele_mu_priv *priv, unsigned int header,
+ uint8_t msg_id, uint8_t sz, bool is_base_api);
+int plat_fill_cmd_msg_hdr(struct ele_mu_priv *priv,
+ struct mu_hdr *hdr,
+ uint8_t cmd,
+ uint32_t len,
+ bool is_base_api);
+#ifdef CONFIG_IMX_ELE_TRNG
+int ele_trng_init(struct device *dev);
+#else
+static inline int ele_trng_init(struct device *dev)
+{
+ return 0;
+}
+#endif
+#endif
diff --git a/drivers/firmware/imx/se_fw.c b/drivers/firmware/imx/se_fw.c
new file mode 100644
index 000000000000..fc06e9076d00
--- /dev/null
+++ b/drivers/firmware/imx/se_fw.c
@@ -0,0 +1,1308 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2021-2023 NXP
+ */
+
+#include <linux/dma-mapping.h>
+#include <linux/completion.h>
+#include <linux/dev_printk.h>
+#include <linux/errno.h>
+#include <linux/export.h>
+#include <linux/firmware/imx/ele_base_msg.h>
+#include <linux/firmware/imx/ele_mu_ioctl.h>
+#include <linux/genalloc.h>
+#include <linux/io.h>
+#include <linux/init.h>
+#include <linux/miscdevice.h>
+#include <linux/mod_devicetable.h>
+#include <linux/module.h>
+#include <linux/of_platform.h>
+#include <linux/of_reserved_mem.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+#include <linux/string.h>
+#include <linux/sys_soc.h>
+
+#include "se_fw.h"
+
+#define SOC_ID_OF_IMX8ULP 0x084D
+#define SOC_ID_OF_IMX93 0x9300
+#define SOC_VER_MASK 0xFFFF0000
+#define SOC_ID_MASK 0x0000FFFF
+#define RESERVED_DMA_POOL BIT(1)
+
+struct imx_info {
+ const uint8_t pdev_name[2][20];
+ bool socdev;
+ uint8_t mu_did;
+ uint8_t max_dev_ctx;
+ uint8_t cmd_tag;
+ uint8_t rsp_tag;
+ uint8_t success_tag;
+ uint8_t base_api_ver;
+ uint8_t fw_api_ver;
+ uint8_t *se_name;
+ uint8_t *mbox_tx_name;
+ uint8_t *mbox_rx_name;
+ uint8_t *pool_name;
+ bool reserved_dma_ranges;
+};
+
+struct imx_info_list {
+ uint8_t num_mu;
+ struct imx_info info[];
+};
+
+static LIST_HEAD(priv_data_list);
+
+static const struct imx_info_list imx8ulp_info = {
+ .num_mu = 1,
+ .info = {
+ {
+ .pdev_name = {"se-fw2", "mu2"},
+ .socdev = true,
+ .mu_did = 7,
+ .max_dev_ctx = 4,
+ .cmd_tag = 0x17,
+ .rsp_tag = 0xe1,
+ .success_tag = 0xd6,
+ .base_api_ver = MESSAGING_VERSION_6,
+ .fw_api_ver = MESSAGING_VERSION_7,
+ .se_name = "ele",
+ .mbox_tx_name = "tx",
+ .mbox_rx_name = "rx",
+ .pool_name = "sram",
+ .reserved_dma_ranges = true,
+ },
+ },
+};
+
+static const struct imx_info_list imx93_info = {
+ .num_mu = 1,
+ .info = {
+ {
+ .pdev_name = {"se-fw2", "mu2"},
+ .socdev = true,
+ .mu_did = 3,
+ .max_dev_ctx = 4,
+ .cmd_tag = 0x17,
+ .rsp_tag = 0xe1,
+ .success_tag = 0xd6,
+ .base_api_ver = MESSAGING_VERSION_6,
+ .fw_api_ver = MESSAGING_VERSION_7,
+ .se_name = "ele",
+ .mbox_tx_name = "tx",
+ .mbox_rx_name = "rx",
+ .pool_name = NULL,
+ .reserved_dma_ranges = true,
+ },
+ },
+};
+
+static const struct of_device_id se_fw_match[] = {
+ { .compatible = "fsl,imx8ulp-se-fw", .data = (void *)&imx8ulp_info},
+ { .compatible = "fsl,imx93-se-fw", .data = (void *)&imx93_info},
+ {},
+};
+
+static struct imx_info *get_imx_info(struct imx_info_list *info_list,
+ const uint8_t *pdev_name,
+ uint8_t len)
+{
+ int i = 0;
+
+ for (i = 0; i < info_list->num_mu; i++)
+ if (!memcmp(info_list->info[i].pdev_name[0], pdev_name, len))
+ return &info_list->info[i];
+
+ return NULL;
+}
+
+/*
+ * Callback called by mailbox FW when data are received
+ */
+static void ele_mu_rx_callback(struct mbox_client *c, void *msg)
+{
+ struct device *dev = c->dev;
+ struct ele_mu_priv *priv = dev_get_drvdata(dev);
+ struct ele_mu_device_ctx *dev_ctx;
+ bool is_response = false;
+ int msg_size;
+ struct mu_hdr header;
+
+ /* The function can be called with NULL msg */
+ if (!msg) {
+ dev_err(dev, "Message is invalid\n");
+ return;
+ }
+
+ header.tag = ((u8 *)msg)[TAG_OFFSET];
+ header.command = ((u8 *)msg)[CMD_OFFSET];
+ header.size = ((u8 *)msg)[SZ_OFFSET];
+ header.ver = ((u8 *)msg)[VER_OFFSET];
+
+ /* Incoming command: wake up the receiver if any. */
+ if (header.tag == priv->cmd_tag) {
+ dev_dbg(dev, "Selecting cmd receiver\n");
+ dev_ctx = priv->cmd_receiver_dev;
+ } else if (header.tag == priv->rsp_tag) {
+ if (priv->waiting_rsp_dev) {
+ dev_dbg(dev, "Selecting rsp waiter\n");
+ dev_ctx = priv->waiting_rsp_dev;
+ is_response = true;
+ } else {
+ /*
+ * Reading the EdgeLock Enclave response
+ * to the command, sent by other
+ * linux kernel services.
+ */
+ spin_lock(&priv->lock);
+ if (priv->rx_msg)
+ memcpy(priv->rx_msg, msg, header.size << 2);
+ else
+ dev_err(dev, "No RX buffer to save response.\n");
+
+ complete(&priv->done);
+ spin_unlock(&priv->lock);
+ return;
+ }
+ } else {
+ dev_err(dev, "Failed to select a device for message: %.8x\n",
+ *((u32 *) &header));
+ return;
+ }
+
+ if (!dev_ctx) {
+ dev_err(dev, "No device context selected for message: %.8x\n",
+ *((u32 *)&header));
+ return;
+ }
+ /* Init reception */
+ msg_size = header.size;
+ if (msg_size > MAX_RECV_SIZE) {
+ dev_err(dev, "%s: Message is too big (%d > %d)",
+ dev_ctx->miscdev.name,
+ msg_size,
+ MAX_RECV_SIZE);
+ return;
+ }
+
+ memcpy(dev_ctx->temp_resp, msg, msg_size << 2);
+ dev_ctx->temp_resp_size = msg_size;
+
+ /* Allow user to read */
+ dev_ctx->pending_hdr = dev_ctx->temp_resp[0];
+ wake_up_interruptible(&dev_ctx->wq);
+
+ if (is_response)
+ priv->waiting_rsp_dev = NULL;
+
+}
+
+phys_addr_t get_phy_buf_mem_pool(struct device *dev,
+ char *mem_pool_name,
+ u32 **buf,
+ uint32_t size)
+{
+ struct device_node *of_node = dev->of_node;
+ struct gen_pool *mem_pool = of_gen_pool_get(of_node,
+ mem_pool_name, 0);
+ if (!mem_pool) {
+ dev_err(dev, "Unable to get sram pool\n");
+ return 0;
+ }
+
+ *buf = (u32 *)gen_pool_alloc(mem_pool, size);
+ if (!buf) {
+ dev_err(dev, "Unable to alloc sram from sram pool\n");
+ return 0;
+ }
+
+ return gen_pool_virt_to_phys(mem_pool, (ulong)*buf);
+}
+
+void free_phybuf_mem_pool(struct device *dev,
+ char *mem_pool_name,
+ u32 *buf,
+ uint32_t size)
+{
+ struct device_node *of_node = dev->of_node;
+ struct gen_pool *mem_pool = of_gen_pool_get(of_node,
+ mem_pool_name, 0);
+
+ if (!mem_pool)
+ dev_err(dev, "%s failed: Unable to get sram pool.\n", __func__);
+
+ gen_pool_free(mem_pool, (unsigned long)buf, size);
+}
+
+static int imx_soc_device_register(struct device *dev,
+ struct imx_info *info)
+{
+ struct soc_device_attribute *attr;
+ struct soc_device *sdev = NULL;
+ phys_addr_t get_info_addr = 0;
+ u32 *get_info_data = NULL;
+ u8 major_ver, minor_ver;
+ int err;
+
+ if (info->pool_name) {
+ get_info_addr = get_phy_buf_mem_pool(dev,
+ info->pool_name,
+ &get_info_data,
+ DEVICE_GET_INFO_SZ);
+ } else {
+ get_info_data = dmam_alloc_coherent(dev,
+ DEVICE_GET_INFO_SZ,
+ &get_info_addr,
+ GFP_KERNEL);
+ }
+ if (!get_info_addr) {
+ dev_err(dev, "Unable to alloc buffer for device info.\n");
+ return -ENOMEM;
+ }
+
+ attr = kzalloc(sizeof(*attr), GFP_KERNEL);
+ if (!attr)
+ return -ENOMEM;
+
+ err = ele_get_info(dev, get_info_addr, ELE_GET_INFO_READ_SZ);
+ if (err) {
+ attr->revision = kasprintf(GFP_KERNEL, "A0");
+ } else {
+ major_ver = (get_info_data[GET_INFO_SOC_INFO_WORD_OFFSET]
+ & SOC_VER_MASK) >> 24;
+ minor_ver = ((get_info_data[GET_INFO_SOC_INFO_WORD_OFFSET]
+ & SOC_VER_MASK) >> 16) & 0xFF;
+ if (minor_ver)
+ attr->revision = kasprintf(GFP_KERNEL,
+ "%x.%x",
+ major_ver,
+ minor_ver);
+ else
+ attr->revision = kasprintf(GFP_KERNEL,
+ "%x",
+ major_ver);
+
+ switch (get_info_data[GET_INFO_SOC_INFO_WORD_OFFSET]
+ & SOC_ID_MASK) {
+ case SOC_ID_OF_IMX8ULP:
+ attr->soc_id = kasprintf(GFP_KERNEL,
+ "i.MX8ULP");
+ break;
+ case SOC_ID_OF_IMX93:
+ attr->soc_id = kasprintf(GFP_KERNEL,
+ "i.MX93");
+ break;
+ }
+ }
+
+ err = of_property_read_string(of_root, "model",
+ &attr->machine);
+ if (err) {
+ kfree(attr);
+ return -EINVAL;
+ }
+ attr->family = kasprintf(GFP_KERNEL, "Freescale i.MX");
+
+ attr->serial_number
+ = kasprintf(GFP_KERNEL, "%016llX",
+ (u64)get_info_data[GET_INFO_SL_NUM_MSB_WORD_OFF] << 32
+ | get_info_data[GET_INFO_SL_NUM_LSB_WORD_OFF]);
+
+ if (info->pool_name) {
+ free_phybuf_mem_pool(dev, info->pool_name,
+ get_info_data, DEVICE_GET_INFO_SZ);
+ } else {
+ dmam_free_coherent(dev,
+ DEVICE_GET_INFO_SZ,
+ get_info_data,
+ get_info_addr);
+ }
+
+ sdev = soc_device_register(attr);
+ if (IS_ERR(sdev)) {
+ kfree(attr->soc_id);
+ kfree(attr->serial_number);
+ kfree(attr->revision);
+ kfree(attr->family);
+ kfree(attr->machine);
+ kfree(attr);
+ return PTR_ERR(sdev);
+ }
+
+ return 0;
+}
+
+/*
+ * File operations for user-space
+ */
+
+/* Write a message to the MU. */
+static ssize_t ele_mu_fops_write(struct file *fp, const char __user *buf,
+ size_t size, loff_t *ppos)
+{
+ struct ele_mu_device_ctx *dev_ctx
+ = container_of(fp->private_data,
+ struct ele_mu_device_ctx,
+ miscdev);
+ struct ele_mu_priv *ele_mu_priv = dev_ctx->priv;
+ u32 nb_words = 0;
+ struct mu_hdr header;
+ int err;
+
+ dev_dbg(ele_mu_priv->dev,
+ "%s: write from buf (%p)%zu, ppos=%lld\n",
+ dev_ctx->miscdev.name,
+ buf, size, ((ppos) ? *ppos : 0));
+
+ if (down_interruptible(&dev_ctx->fops_lock))
+ return -EBUSY;
+
+ if (dev_ctx->status != MU_OPENED) {
+ err = -EINVAL;
+ goto exit;
+ }
+
+ if (size < ELE_MU_HDR_SZ) {
+ dev_err(ele_mu_priv->dev,
+ "%s: User buffer too small(%zu < %d)\n",
+ dev_ctx->miscdev.name,
+ size, ELE_MU_HDR_SZ);
+ err = -ENOSPC;
+ goto exit;
+ }
+
+ if (size > MAX_MESSAGE_SIZE_BYTES) {
+ dev_err(ele_mu_priv->dev,
+ "%s: User buffer too big(%zu > %d)\n",
+ dev_ctx->miscdev.name,
+ size,
+ MAX_MESSAGE_SIZE_BYTES);
+ err = -ENOSPC;
+ goto exit;
+ }
+
+ /* Copy data to buffer */
+ if (copy_from_user(dev_ctx->temp_cmd, buf, size)) {
+ err = -EFAULT;
+ dev_err(ele_mu_priv->dev,
+ "%s: Fail copy message from user\n",
+ dev_ctx->miscdev.name);
+ goto exit;
+ }
+
+ print_hex_dump_debug("from user ", DUMP_PREFIX_OFFSET, 4, 4,
+ dev_ctx->temp_cmd, size, false);
+
+ header = *((struct mu_hdr *) (&dev_ctx->temp_cmd[0]));
+
+ /* Check the message is valid according to tags */
+ if (header.tag == ele_mu_priv->cmd_tag) {
+ /*
+ * Command-lock will be unlocked in ele_mu_fops_read
+ * when the response to this command, is read.
+ *
+ * This command lock is taken to serialize
+ * the command execution over an MU.
+ *
+ * A command execution considered completed, when the
+ * response to the command is received.
+ */
+ mutex_lock(&ele_mu_priv->mu_cmd_lock);
+ ele_mu_priv->waiting_rsp_dev = dev_ctx;
+ } else if (header.tag == ele_mu_priv->rsp_tag) {
+ /* Check the device context can send the command */
+ if (dev_ctx != ele_mu_priv->cmd_receiver_dev) {
+ dev_err(ele_mu_priv->dev,
+ "%s: Channel not configured to send resp to FW.",
+ dev_ctx->miscdev.name);
+ err = -EPERM;
+ goto exit;
+ }
+ } else {
+ dev_err(ele_mu_priv->dev,
+ "%s: The message does not have a valid TAG\n",
+ dev_ctx->miscdev.name);
+ err = -EINVAL;
+ goto exit;
+ }
+
+ /*
+ * Check that the size passed as argument matches the size
+ * carried in the message.
+ */
+ nb_words = header.size;
+ if (nb_words << 2 != size) {
+ dev_err(ele_mu_priv->dev,
+ "%s: User buffer too small\n",
+ dev_ctx->miscdev.name);
+ goto exit;
+ }
+
+ mutex_lock(&ele_mu_priv->mu_lock);
+
+ /* Send message */
+ dev_dbg(ele_mu_priv->dev,
+ "%s: sending message\n",
+ dev_ctx->miscdev.name);
+ err = mbox_send_message(ele_mu_priv->tx_chan, dev_ctx->temp_cmd);
+ if (err < 0) {
+ dev_err(ele_mu_priv->dev,
+ "%s: Failed to send message\n",
+ dev_ctx->miscdev.name);
+ goto unlock;
+ }
+
+ err = nb_words << 2;
+
+unlock:
+ mutex_unlock(&ele_mu_priv->mu_lock);
+
+exit:
+ if (err < 0)
+ mutex_unlock(&ele_mu_priv->mu_cmd_lock);
+ up(&dev_ctx->fops_lock);
+ return err;
+}
+
+/*
+ * Read a message from the MU.
+ * Blocking until a message is available.
+ */
+static ssize_t ele_mu_fops_read(struct file *fp, char __user *buf,
+ size_t size, loff_t *ppos)
+{
+ struct ele_mu_device_ctx *dev_ctx
+ = container_of(fp->private_data,
+ struct ele_mu_device_ctx,
+ miscdev);
+ struct ele_mu_priv *ele_mu_priv = dev_ctx->priv;
+ u32 data_size = 0, size_to_copy = 0;
+ struct ele_buf_desc *b_desc;
+ int err;
+ struct mu_hdr header = {0};
+
+ dev_dbg(ele_mu_priv->dev,
+ "%s: read to buf %p(%zu), ppos=%lld\n",
+ dev_ctx->miscdev.name,
+ buf, size, ((ppos) ? *ppos : 0));
+
+ if (down_interruptible(&dev_ctx->fops_lock))
+ return -EBUSY;
+
+ if (dev_ctx->status != MU_OPENED) {
+ err = -EINVAL;
+ goto exit;
+ }
+
+ /* Wait until the complete message is received on the MU. */
+ err = wait_event_interruptible(dev_ctx->wq, dev_ctx->pending_hdr != 0);
+ if (err) {
+ dev_err(ele_mu_priv->dev,
+ "%s: Err[0x%x]:Interrupted by signal.\n",
+ dev_ctx->miscdev.name, err);
+ goto exit;
+ }
+
+ dev_dbg(ele_mu_priv->dev,
+ "%s: %s %s\n",
+ dev_ctx->miscdev.name,
+ __func__,
+ "message received, start transmit to user");
+
+ /*
+ * Check that the size passed as argument is larger than
+ * the one carried in the message.
+ */
+ data_size = dev_ctx->temp_resp_size << 2;
+ size_to_copy = data_size;
+ if (size_to_copy > size) {
+ dev_dbg(ele_mu_priv->dev,
+ "%s: User buffer too small (%zu < %d)\n",
+ dev_ctx->miscdev.name,
+ size, size_to_copy);
+ size_to_copy = size;
+ }
+
+ /*
+ * We may need to copy the output data to user before
+ * delivering the completion message.
+ */
+ while (!list_empty(&dev_ctx->pending_out)) {
+ b_desc = list_first_entry_or_null(&dev_ctx->pending_out,
+ struct ele_buf_desc,
+ link);
+ if (!b_desc)
+ continue;
+
+ if (b_desc->usr_buf_ptr && b_desc->shared_buf_ptr) {
+
+ dev_dbg(ele_mu_priv->dev,
+ "%s: Copy output data to user\n",
+ dev_ctx->miscdev.name);
+ if (copy_to_user(b_desc->usr_buf_ptr,
+ b_desc->shared_buf_ptr,
+ b_desc->size)) {
+ dev_err(ele_mu_priv->dev,
+ "%s: Failure copying output data to user.",
+ dev_ctx->miscdev.name);
+ err = -EFAULT;
+ goto exit;
+ }
+ }
+
+ if (b_desc->shared_buf_ptr)
+ memset(b_desc->shared_buf_ptr, 0, b_desc->size);
+
+ __list_del_entry(&b_desc->link);
+ devm_kfree(dev_ctx->dev, b_desc);
+ }
+
+ header = *((struct mu_hdr *) (&dev_ctx->temp_resp[0]));
+
+ /* Copy data from the buffer */
+ print_hex_dump_debug("to user ", DUMP_PREFIX_OFFSET, 4, 4,
+ dev_ctx->temp_resp, size_to_copy, false);
+ if (copy_to_user(buf, dev_ctx->temp_resp, size_to_copy)) {
+ dev_err(ele_mu_priv->dev,
+ "%s: Failed to copy to user\n",
+ dev_ctx->miscdev.name);
+ err = -EFAULT;
+ goto exit;
+ }
+
+ err = size_to_copy;
+
+ /* free memory allocated on the shared buffers. */
+ dev_ctx->secure_mem.pos = 0;
+ dev_ctx->non_secure_mem.pos = 0;
+
+ dev_ctx->pending_hdr = 0;
+
+exit:
+ /*
+ * Clean the used Shared Memory space,
+ * whether its Input Data copied from user buffers, or
+ * Data received from FW.
+ */
+ while (!list_empty(&dev_ctx->pending_in) ||
+ !list_empty(&dev_ctx->pending_out)) {
+ if (!list_empty(&dev_ctx->pending_in))
+ b_desc = list_first_entry_or_null(&dev_ctx->pending_in,
+ struct ele_buf_desc,
+ link);
+ else
+ b_desc = list_first_entry_or_null(&dev_ctx->pending_out,
+ struct ele_buf_desc,
+ link);
+
+ if (!b_desc)
+ continue;
+
+ if (b_desc->shared_buf_ptr)
+ memset(b_desc->shared_buf_ptr, 0, b_desc->size);
+
+ __list_del_entry(&b_desc->link);
+ devm_kfree(dev_ctx->dev, b_desc);
+ }
+ if (header.tag == ele_mu_priv->rsp_tag)
+ mutex_unlock(&ele_mu_priv->mu_cmd_lock);
+
+ up(&dev_ctx->fops_lock);
+ return err;
+}
+
+/* Give access to EdgeLock Enclave, to the memory we want to share */
+static int ele_mu_setup_ele_mem_access(struct ele_mu_device_ctx *dev_ctx,
+ u64 addr, u32 len)
+{
+ /* Assuming EdgeLock Enclave has access to all the memory regions */
+ int ret = 0;
+
+ if (ret) {
+ dev_err(dev_ctx->priv->dev,
+ "%s: Fail find memreg\n", dev_ctx->miscdev.name);
+ goto exit;
+ }
+
+ if (ret) {
+ dev_err(dev_ctx->priv->dev,
+ "%s: Fail set permission for resource\n",
+ dev_ctx->miscdev.name);
+ goto exit;
+ }
+
+exit:
+ return ret;
+}
+
+static int ele_mu_ioctl_get_mu_info(struct ele_mu_device_ctx *dev_ctx,
+ unsigned long arg)
+{
+ struct ele_mu_priv *priv = dev_get_drvdata(dev_ctx->dev);
+ struct ele_mu_ioctl_get_mu_info info;
+ int err = -EINVAL;
+
+ info.ele_mu_id = 0;
+ info.interrupt_idx = 0;
+ info.tz = 0;
+ info.did = priv->ele_mu_did;
+
+ dev_dbg(priv->dev,
+ "%s: info [mu_idx: %d, irq_idx: %d, tz: 0x%x, did: 0x%x]\n",
+ dev_ctx->miscdev.name,
+ info.ele_mu_id, info.interrupt_idx, info.tz, info.did);
+
+ if (copy_to_user((u8 *)arg, &info, sizeof(info))) {
+ dev_err(dev_ctx->priv->dev,
+ "%s: Failed to copy mu info to user\n",
+ dev_ctx->miscdev.name);
+ err = -EFAULT;
+ goto exit;
+ }
+
+exit:
+ return err;
+}
+
+/*
+ * Copy a buffer of data to/from the user and return the address to use in
+ * messages
+ */
+static int ele_mu_ioctl_setup_iobuf_handler(struct ele_mu_device_ctx *dev_ctx,
+ unsigned long arg)
+{
+ struct ele_buf_desc *b_desc;
+ struct ele_mu_ioctl_setup_iobuf io = {0};
+ struct ele_shared_mem *shared_mem;
+ int err = 0;
+ u32 pos;
+
+ if (copy_from_user(&io, (u8 *)arg, sizeof(io))) {
+ dev_err(dev_ctx->priv->dev,
+ "%s: Failed copy iobuf config from user\n",
+ dev_ctx->miscdev.name);
+ err = -EFAULT;
+ goto exit;
+ }
+
+ dev_dbg(dev_ctx->priv->dev,
+ "%s: io [buf: %p(%d) flag: %x]\n",
+ dev_ctx->miscdev.name,
+ io.user_buf, io.length, io.flags);
+
+ if (io.length == 0 || !io.user_buf) {
+ /*
+ * Accept NULL pointers since some buffers are optional
+ * in FW commands. In this case we should return 0 as
+ * pointer to be embedded into the message.
+ * Skip all data copy part of code below.
+ */
+ io.ele_addr = 0;
+ goto copy;
+ }
+
+ /* Select the shared memory to be used for this buffer. */
+ if (io.flags & ELE_MU_IO_FLAGS_USE_SEC_MEM) {
+ /* App requires to use secure memory for this buffer.*/
+ dev_err(dev_ctx->priv->dev,
+ "%s: Failed allocate SEC MEM memory\n",
+ dev_ctx->miscdev.name);
+ err = -EFAULT;
+ goto exit;
+ } else {
+ /* No specific requirement for this buffer. */
+ shared_mem = &dev_ctx->non_secure_mem;
+ }
+
+ /* Check there is enough space in the shared memory. */
+ if (shared_mem->size < shared_mem->pos
+ || io.length >= shared_mem->size - shared_mem->pos) {
+ dev_err(dev_ctx->priv->dev,
+ "%s: Not enough space in shared memory\n",
+ dev_ctx->miscdev.name);
+ err = -ENOMEM;
+ goto exit;
+ }
+
+ /* Allocate space in shared memory. 8 bytes aligned. */
+ pos = shared_mem->pos;
+ shared_mem->pos += round_up(io.length, 8u);
+ io.ele_addr = (u64)shared_mem->dma_addr + pos;
+
+ if ((io.flags & ELE_MU_IO_FLAGS_USE_SEC_MEM) &&
+ !(io.flags & ELE_MU_IO_FLAGS_USE_SHORT_ADDR)) {
+ /*Add base address to get full address.*/
+ dev_err(dev_ctx->priv->dev,
+ "%s: Failed allocate SEC MEM memory\n",
+ dev_ctx->miscdev.name);
+ err = -EFAULT;
+ goto exit;
+ }
+
+ memset(shared_mem->ptr + pos, 0, io.length);
+ if ((io.flags & ELE_MU_IO_FLAGS_IS_INPUT) ||
+ (io.flags & ELE_MU_IO_FLAGS_IS_IN_OUT)) {
+ /*
+ * buffer is input:
+ * copy data from user space to this allocated buffer.
+ */
+ if (copy_from_user(shared_mem->ptr + pos, io.user_buf,
+ io.length)) {
+ dev_err(dev_ctx->priv->dev,
+ "%s: Failed copy data to shared memory\n",
+ dev_ctx->miscdev.name);
+ err = -EFAULT;
+ goto exit;
+ }
+ }
+
+ b_desc = devm_kmalloc(dev_ctx->dev, sizeof(*b_desc), GFP_KERNEL);
+ if (!b_desc) {
+ err = -ENOMEM;
+ dev_err(dev_ctx->priv->dev,
+ "%s: Failed allocating mem for pending buffer\n",
+ dev_ctx->miscdev.name);
+ goto exit;
+ }
+
+ b_desc->shared_buf_ptr = shared_mem->ptr + pos;
+ b_desc->usr_buf_ptr = io.user_buf;
+ b_desc->size = io.length;
+
+ if (io.flags & ELE_MU_IO_FLAGS_IS_INPUT) {
+ /*
+ * buffer is input:
+ * add an entry in the "pending input buffers" list so
+ * that copied data can be cleaned from shared memory
+ * later.
+ */
+ list_add_tail(&b_desc->link, &dev_ctx->pending_in);
+ } else {
+ /*
+ * buffer is output:
+ * add an entry in the "pending out buffers" list so data
+ * can be copied to user space when receiving ELE
+ * response.
+ */
+ list_add_tail(&b_desc->link, &dev_ctx->pending_out);
+ }
+
+copy:
+ /* Provide the EdgeLock Enclave address to user space only if success.*/
+ if (copy_to_user((u8 *)arg, &io, sizeof(io))) {
+ dev_err(dev_ctx->priv->dev,
+ "%s: Failed to copy iobuff setup to user\n",
+ dev_ctx->miscdev.name);
+ err = -EFAULT;
+ goto exit;
+ }
+exit:
+ return err;
+}
+
+/* Open a char device. */
+static int ele_mu_fops_open(struct inode *nd, struct file *fp)
+{
+ struct ele_mu_device_ctx *dev_ctx
+ = container_of(fp->private_data,
+ struct ele_mu_device_ctx,
+ miscdev);
+ int err;
+
+ /* Avoid race if opened at the same time */
+ if (down_trylock(&dev_ctx->fops_lock))
+ return -EBUSY;
+
+ /* Authorize only 1 instance. */
+ if (dev_ctx->status != MU_FREE) {
+ err = -EBUSY;
+ goto exit;
+ }
+
+ /*
+ * Allocate some memory for data exchanges with S40x.
+ * This will be used for data not requiring secure memory.
+ */
+ dev_ctx->non_secure_mem.ptr = dmam_alloc_coherent(dev_ctx->dev,
+ MAX_DATA_SIZE_PER_USER,
+ &dev_ctx->non_secure_mem.dma_addr,
+ GFP_KERNEL);
+ if (!dev_ctx->non_secure_mem.ptr) {
+ err = -ENOMEM;
+ dev_err(dev_ctx->priv->dev,
+ "%s: Failed to map shared memory with FW.\n",
+ dev_ctx->miscdev.name);
+ goto exit;
+ }
+
+ err = ele_mu_setup_ele_mem_access(dev_ctx,
+ dev_ctx->non_secure_mem.dma_addr,
+ MAX_DATA_SIZE_PER_USER);
+ if (err) {
+ err = -EPERM;
+ dev_err(dev_ctx->priv->dev,
+ "%s: Failed to share access to shared memory\n",
+ dev_ctx->miscdev.name);
+ goto free_coherent;
+ }
+
+ dev_ctx->non_secure_mem.size = MAX_DATA_SIZE_PER_USER;
+ dev_ctx->non_secure_mem.pos = 0;
+ dev_ctx->status = MU_OPENED;
+
+ dev_ctx->pending_hdr = 0;
+
+ goto exit;
+
+free_coherent:
+ dmam_free_coherent(dev_ctx->priv->dev, MAX_DATA_SIZE_PER_USER,
+ dev_ctx->non_secure_mem.ptr,
+ dev_ctx->non_secure_mem.dma_addr);
+
+exit:
+ up(&dev_ctx->fops_lock);
+ return err;
+}
+
+/* Close a char device. */
+static int ele_mu_fops_close(struct inode *nd, struct file *fp)
+{
+ struct ele_mu_device_ctx *dev_ctx = container_of(fp->private_data,
+ struct ele_mu_device_ctx, miscdev);
+ struct ele_mu_priv *priv = dev_ctx->priv;
+ struct ele_buf_desc *b_desc;
+
+ /* Avoid race if closed at the same time */
+ if (down_trylock(&dev_ctx->fops_lock))
+ return -EBUSY;
+
+ /* The device context has not been opened */
+ if (dev_ctx->status != MU_OPENED)
+ goto exit;
+
+ /* check if this device was registered as command receiver. */
+ if (priv->cmd_receiver_dev == dev_ctx)
+ priv->cmd_receiver_dev = NULL;
+
+ /* check if this device was registered as waiting response. */
+ if (priv->waiting_rsp_dev == dev_ctx) {
+ priv->waiting_rsp_dev = NULL;
+ mutex_unlock(&priv->mu_cmd_lock);
+ }
+
+ /* Unmap secure memory shared buffer. */
+ if (dev_ctx->secure_mem.ptr)
+ devm_iounmap(dev_ctx->dev, dev_ctx->secure_mem.ptr);
+
+ dev_ctx->secure_mem.ptr = NULL;
+ dev_ctx->secure_mem.dma_addr = 0;
+ dev_ctx->secure_mem.size = 0;
+ dev_ctx->secure_mem.pos = 0;
+
+ /* Free non-secure shared buffer. */
+ dmam_free_coherent(dev_ctx->priv->dev, MAX_DATA_SIZE_PER_USER,
+ dev_ctx->non_secure_mem.ptr,
+ dev_ctx->non_secure_mem.dma_addr);
+
+ dev_ctx->non_secure_mem.ptr = NULL;
+ dev_ctx->non_secure_mem.dma_addr = 0;
+ dev_ctx->non_secure_mem.size = 0;
+ dev_ctx->non_secure_mem.pos = 0;
+
+ while (!list_empty(&dev_ctx->pending_in) ||
+ !list_empty(&dev_ctx->pending_out)) {
+ if (!list_empty(&dev_ctx->pending_in))
+ b_desc = list_first_entry_or_null(&dev_ctx->pending_in,
+ struct ele_buf_desc,
+ link);
+ else
+ b_desc = list_first_entry_or_null(&dev_ctx->pending_out,
+ struct ele_buf_desc,
+ link);
+
+ if (!b_desc)
+ continue;
+
+ if (b_desc->shared_buf_ptr)
+ memset(b_desc->shared_buf_ptr, 0, b_desc->size);
+
+ __list_del_entry(&b_desc->link);
+ devm_kfree(dev_ctx->dev, b_desc);
+ }
+
+ dev_ctx->status = MU_FREE;
+
+exit:
+ up(&dev_ctx->fops_lock);
+ return 0;
+}
+
+/* IOCTL entry point of a char device */
+static long ele_mu_ioctl(struct file *fp, unsigned int cmd, unsigned long arg)
+{
+ struct ele_mu_device_ctx *dev_ctx
+ = container_of(fp->private_data,
+ struct ele_mu_device_ctx,
+ miscdev);
+ struct ele_mu_priv *ele_mu_priv = dev_ctx->priv;
+ int err = -EINVAL;
+
+ /* Prevent race during change of device context */
+ if (down_interruptible(&dev_ctx->fops_lock))
+ return -EBUSY;
+
+ switch (cmd) {
+ case ELE_MU_IOCTL_ENABLE_CMD_RCV:
+ if (!ele_mu_priv->cmd_receiver_dev) {
+ ele_mu_priv->cmd_receiver_dev = dev_ctx;
+ err = 0;
+ }
+ break;
+ case ELE_MU_IOCTL_GET_MU_INFO:
+ err = ele_mu_ioctl_get_mu_info(dev_ctx, arg);
+ break;
+ case ELE_MU_IOCTL_SETUP_IOBUF:
+ err = ele_mu_ioctl_setup_iobuf_handler(dev_ctx, arg);
+ break;
+ default:
+ err = -EINVAL;
+ dev_dbg(ele_mu_priv->dev,
+ "%s: IOCTL %.8x not supported\n",
+ dev_ctx->miscdev.name,
+ cmd);
+ }
+
+ up(&dev_ctx->fops_lock);
+ return (long)err;
+}
+
+/* Char driver setup */
+static const struct file_operations ele_mu_fops = {
+ .open = ele_mu_fops_open,
+ .owner = THIS_MODULE,
+ .release = ele_mu_fops_close,
+ .unlocked_ioctl = ele_mu_ioctl,
+ .read = ele_mu_fops_read,
+ .write = ele_mu_fops_write,
+};
+
+/* interface for managed res to free a mailbox channel */
+static void if_mbox_free_channel(void *mbox_chan)
+{
+ mbox_free_channel(mbox_chan);
+}
+
+/* interface for managed res to unregister a char device */
+static void if_misc_deregister(void *miscdevice)
+{
+ misc_deregister(miscdevice);
+}
+
+static int ele_mu_request_channel(struct device *dev,
+ struct mbox_chan **chan,
+ struct mbox_client *cl,
+ const char *name)
+{
+ struct mbox_chan *t_chan;
+ int ret = 0;
+
+ t_chan = mbox_request_channel_byname(cl, name);
+ if (IS_ERR(t_chan)) {
+ ret = PTR_ERR(t_chan);
+ if (ret != -EPROBE_DEFER)
+ dev_err(dev,
+ "Failed to request chan %s ret %d\n", name,
+ ret);
+ goto exit;
+ }
+
+ ret = devm_add_action(dev, if_mbox_free_channel, t_chan);
+ if (ret) {
+ dev_err(dev, "failed to add devm removal of mbox %s\n", name);
+ goto exit;
+ }
+
+ *chan = t_chan;
+
+exit:
+ return ret;
+}
+
+static int se_probe_cleanup(struct platform_device *pdev)
+{
+ int ret;
+ int i;
+ struct device *dev = &pdev->dev;
+ struct ele_mu_priv *priv;
+
+ priv = dev_get_drvdata(dev);
+
+ if (!priv) {
+ ret = -EINVAL;
+ dev_err(dev, "Invalid ELE-MU Priv data");
+ return ret;
+ }
+
+ if (priv->tx_chan)
+ mbox_free_channel(priv->tx_chan);
+ if (priv->rx_chan)
+ mbox_free_channel(priv->rx_chan);
+
+ if (priv->flags & RESERVED_DMA_POOL) {
+ of_reserved_mem_device_release(dev);
+ priv->flags &= (~RESERVED_DMA_POOL);
+ }
+
+ if (priv->ctxs) {
+ for (i = 0; i < priv->max_dev_ctx; i++) {
+ if (priv->ctxs[i])
+ devm_kfree(dev, priv->ctxs[i]);
+ }
+ devm_kfree(dev, priv->ctxs);
+ }
+
+ __list_del_entry(&priv->priv_data);
+
+ devm_kfree(dev, priv);
+ return ret;
+}
+
+static int se_fw_probe(struct platform_device *pdev)
+{
+ struct ele_mu_device_ctx *dev_ctx;
+ struct device *dev = &pdev->dev;
+ struct ele_mu_priv *priv;
+ const struct of_device_id *of_id = of_match_device(se_fw_match, dev);
+ struct imx_info *info = NULL;
+ char *devname;
+ int ret;
+ int i;
+ struct device_node *np;
+
+ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+ if (!priv) {
+ ret = -ENOMEM;
+ dev_dbg(dev, "Fail allocate mem for private data\n");
+ return ret;
+ }
+ memset(priv, 0x0, sizeof(*priv));
+ priv->dev = dev;
+ dev_set_drvdata(dev, priv);
+
+ list_add_tail(&priv->priv_data, &priv_data_list);
+
+ /*
+ * Get the address of MU.
+ */
+ np = pdev->dev.of_node;
+ if (!np) {
+ dev_dbg(dev, "Cannot find entry in device tree\n");
+ ret = -EOPNOTSUPP;
+ goto exit;
+ }
+
+ /* Initialize the mutex. */
+ mutex_init(&priv->mu_cmd_lock);
+ mutex_init(&priv->mu_lock);
+
+ priv->cmd_receiver_dev = NULL;
+ priv->waiting_rsp_dev = NULL;
+
+ /* Mailbox client configuration */
+ priv->ele_mb_cl.dev = dev;
+ priv->ele_mb_cl.tx_block = false;
+ priv->ele_mb_cl.knows_txdone = true;
+ priv->ele_mb_cl.rx_callback = ele_mu_rx_callback;
+
+ info = get_imx_info((struct imx_info_list *)of_id->data,
+ pdev->name, strlen(pdev->name) + 1);
+
+ if (!info) {
+ dev_dbg(dev, "Cannot find matching dev-info.\n");
+ ret = -EOPNOTSUPP;
+ goto exit;
+ }
+
+ priv->info = info;
+ memcpy(priv->pdev_name, pdev->name, strlen(pdev->name) + 1);
+ priv->max_dev_ctx = info->max_dev_ctx;
+ priv->cmd_tag = info->cmd_tag;
+ priv->rsp_tag = info->rsp_tag;
+ priv->success_tag = info->success_tag;
+ priv->base_api_ver = info->base_api_ver;
+ priv->fw_api_ver = info->fw_api_ver;
+
+ ret = ele_mu_request_channel(dev, &priv->tx_chan,
+ &priv->ele_mb_cl, info->mbox_tx_name);
+ if (ret) {
+ if (ret == -EPROBE_DEFER)
+ dev_dbg(dev, "Mailbox tx channel, is not ready.\n");
+ else
+ dev_dbg(dev, "Failed to request tx channel\n");
+
+ goto exit;
+ }
+
+ ret = ele_mu_request_channel(dev, &priv->rx_chan,
+ &priv->ele_mb_cl, info->mbox_rx_name);
+ if (ret) {
+ if (ret == -EPROBE_DEFER)
+ dev_dbg(dev, "Mailbox rx channel, is not ready.\n");
+ else
+ dev_dbg(dev, "Failed to request rx channel\n");
+
+ goto exit;
+ }
+
+ priv->ctxs = devm_kzalloc(dev, sizeof(dev_ctx) * priv->max_dev_ctx,
+ GFP_KERNEL);
+
+ if (!priv->ctxs) {
+ ret = -ENOMEM;
+ dev_dbg(dev, "Fail allocate mem for private dev-ctxs.\n");
+ goto exit;
+ }
+
+ /* Create users */
+ for (i = 0; i < priv->max_dev_ctx; i++) {
+ dev_ctx = devm_kzalloc(dev, sizeof(*dev_ctx), GFP_KERNEL);
+ if (!dev_ctx) {
+ ret = -ENOMEM;
+ dev_dbg(dev,
+ "Fail to allocate memory for device context\n");
+ goto exit;
+ }
+
+ dev_ctx->dev = dev;
+ dev_ctx->status = MU_FREE;
+ dev_ctx->priv = priv;
+
+ priv->ctxs[i] = dev_ctx;
+
+ /* Default value invalid for an header. */
+ init_waitqueue_head(&dev_ctx->wq);
+
+ INIT_LIST_HEAD(&dev_ctx->pending_out);
+ INIT_LIST_HEAD(&dev_ctx->pending_in);
+ sema_init(&dev_ctx->fops_lock, 1);
+
+ devname = devm_kasprintf(dev, GFP_KERNEL, "%s_%s_ch%d",
+ info->se_name,
+ info->pdev_name[1], i);
+ if (!devname) {
+ ret = -ENOMEM;
+ dev_dbg(dev,
+ "Fail to allocate memory for misc dev name\n");
+ goto exit;
+ }
+
+ dev_ctx->miscdev.name = devname;
+ dev_ctx->miscdev.minor = MISC_DYNAMIC_MINOR;
+ dev_ctx->miscdev.fops = &ele_mu_fops;
+ dev_ctx->miscdev.parent = dev;
+ ret = misc_register(&dev_ctx->miscdev);
+ if (ret) {
+ dev_err(dev, "failed to register misc device %d\n",
+ ret);
+ goto exit;
+ }
+
+ ret = devm_add_action(dev, if_misc_deregister,
+ &dev_ctx->miscdev);
+ if (ret) {
+ dev_err(dev,
+ "failed[%d] to add action to the misc-dev\n",
+ ret);
+ goto exit;
+ }
+ }
+
+ init_completion(&priv->done);
+ spin_lock_init(&priv->lock);
+
+ dev_set_drvdata(dev, priv);
+
+ if (info->reserved_dma_ranges) {
+ ret = of_reserved_mem_device_init(dev);
+ if (ret) {
+ dev_err(dev,
+ "failed to init reserved memory region %d\n",
+ ret);
+ priv->flags &= (~RESERVED_DMA_POOL);
+ goto exit;
+ }
+ priv->flags |= RESERVED_DMA_POOL;
+ }
+
+ if (info->socdev) {
+ ret = imx_soc_device_register(dev, info);
+ if (ret) {
+ dev_err(dev,
+ "failed[%d] to register SoC device\n", ret);
+ goto exit;
+ }
+ }
+
+ ret = ele_ping(dev);
+ if (ret)
+ dev_err(dev, "Failed[%d] to ping the fw.\n", ret);
+
+ dev_info(dev, "i.MX secure-enclave: %s interface to firmware, configured.\n",
+ info->pdev_name[1]);
+
+ return devm_of_platform_populate(dev);
+
+exit:
+ /* if execution control reaches here, ele-mu probe fail.
+ * hence doing the cleanup
+ */
+ return se_probe_cleanup(pdev);
+}
+
+static int se_fw_remove(struct platform_device *pdev)
+{
+ se_probe_cleanup(pdev);
+
+ return 0;
+}
+
+#ifdef CONFIG_PM_SLEEP
+static int se_fw_suspend(struct device *dev)
+{
+ return 0;
+}
+
+static int se_fw_resume(struct device *dev)
+{
+ struct ele_mu_priv *priv = dev_get_drvdata(dev);
+ int i;
+
+ for (i = 0; i < priv->max_dev_ctx; i++)
+ wake_up_interruptible(&priv->ctxs[i]->wq);
+
+ return 0;
+}
+#endif
+
+static const struct dev_pm_ops se_fw_pm = {
+ SET_SYSTEM_SLEEP_PM_OPS(se_fw_suspend, se_fw_resume)
+};
+
+static struct platform_driver se_fw_driver = {
+ .driver = {
+ .name = "fsl-se-fw",
+ .of_match_table = se_fw_match,
+ .pm = &se_fw_pm,
+ },
+ .probe = se_fw_probe,
+ .remove = se_fw_remove,
+};
+MODULE_DEVICE_TABLE(of, se_fw_match);
+
+module_platform_driver(se_fw_driver);
+
+MODULE_AUTHOR("Pankaj Gupta <[email protected]>");
+MODULE_DESCRIPTION("iMX Secure Enclave FW Driver.");
+MODULE_LICENSE("GPL");
diff --git a/drivers/firmware/imx/se_fw.h b/drivers/firmware/imx/se_fw.h
new file mode 100644
index 000000000000..c7d7eaec199b
--- /dev/null
+++ b/drivers/firmware/imx/se_fw.h
@@ -0,0 +1,154 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2021-2023 NXP
+ */
+
+#ifndef SE_MU_H
+#define SE_MU_H
+
+#include <linux/miscdevice.h>
+#include <linux/semaphore.h>
+#include <linux/mailbox_client.h>
+
+#define MAX_MESSAGE_SIZE 31
+#define MAX_RECV_SIZE MAX_MESSAGE_SIZE
+#define MAX_RECV_SIZE_BYTES (MAX_RECV_SIZE << 2)
+#define MAX_MESSAGE_SIZE_BYTES (MAX_MESSAGE_SIZE << 2)
+
+#define ELE_MSG_DATA_NUM 10
+
+#define MSG_TAG(x) (((x) & 0xff000000) >> 24)
+#define MSG_COMMAND(x) (((x) & 0x00ff0000) >> 16)
+#define MSG_SIZE(x) (((x) & 0x0000ff00) >> 8)
+#define MSG_VER(x) ((x) & 0x000000ff)
+#define RES_STATUS(x) ((x) & 0x000000ff)
+#define MAX_DATA_SIZE_PER_USER (65 * 1024)
+#define S4_DEFAULT_MUAP_INDEX (2)
+#define S4_MUAP_DEFAULT_MAX_USERS (4)
+#define MESSAGING_VERSION_6 0x6
+#define MESSAGING_VERSION_7 0x7
+
+#define DEFAULT_MESSAGING_TAG_COMMAND (0x17u)
+#define DEFAULT_MESSAGING_TAG_RESPONSE (0xe1u)
+
+#define ELE_MU_IO_FLAGS_USE_SEC_MEM (0x02u)
+#define ELE_MU_IO_FLAGS_USE_SHORT_ADDR (0x04u)
+
+struct ele_imem_buf {
+ u8 *buf;
+ phys_addr_t phyaddr;
+ u32 size;
+};
+
+struct ele_buf_desc {
+ u8 *shared_buf_ptr;
+ u8 *usr_buf_ptr;
+ u32 size;
+ struct list_head link;
+};
+
+/* Status of a char device */
+enum mu_device_status_t {
+ MU_FREE,
+ MU_OPENED
+};
+
+struct ele_shared_mem {
+ dma_addr_t dma_addr;
+ u32 size;
+ u32 pos;
+ u8 *ptr;
+};
+
+/* Private struct for each char device instance. */
+struct ele_mu_device_ctx {
+ struct device *dev;
+ struct ele_mu_priv *priv;
+ struct miscdevice miscdev;
+
+ enum mu_device_status_t status;
+ wait_queue_head_t wq;
+ struct semaphore fops_lock;
+
+ u32 pending_hdr;
+ struct list_head pending_in;
+ struct list_head pending_out;
+
+ struct ele_shared_mem secure_mem;
+ struct ele_shared_mem non_secure_mem;
+
+ u32 temp_cmd[MAX_MESSAGE_SIZE];
+ u32 temp_resp[MAX_RECV_SIZE];
+ u32 temp_resp_size;
+ struct notifier_block ele_notify;
+};
+
+/* Header of the messages exchange with the EdgeLock Enclave */
+struct mu_hdr {
+ u8 ver;
+ u8 size;
+ u8 command;
+ u8 tag;
+} __packed;
+
+#define ELE_MU_HDR_SZ 4
+#define TAG_OFFSET (ELE_MU_HDR_SZ - 1)
+#define CMD_OFFSET (ELE_MU_HDR_SZ - 2)
+#define SZ_OFFSET (ELE_MU_HDR_SZ - 3)
+#define VER_OFFSET (ELE_MU_HDR_SZ - 4)
+
+struct ele_api_msg {
+ u32 header; /* u8 Tag; u8 Command; u8 Size; u8 Ver; */
+ u32 data[ELE_MSG_DATA_NUM];
+};
+
+struct ele_mu_priv {
+ struct list_head priv_data;
+ struct ele_mu_device_ctx *cmd_receiver_dev;
+ struct ele_mu_device_ctx *waiting_rsp_dev;
+ /*
+ * prevent parallel access to the MU registers
+ * e.g. a user trying to send a command while the other one is
+ * sending a response.
+ */
+ struct mutex mu_lock;
+ /*
+ * prevent a command to be sent on the MU while another one is still
+ * processing. (response to a command is allowed)
+ */
+ struct mutex mu_cmd_lock;
+ struct device *dev;
+ u8 ele_mu_did;
+ u8 pdev_name[20];
+ u32 ele_mu_id;
+ u8 cmd_tag;
+ u8 rsp_tag;
+ u8 success_tag;
+ u8 base_api_ver;
+ u8 fw_api_ver;
+ const void *info;
+
+ struct mbox_client ele_mb_cl;
+ struct mbox_chan *tx_chan, *rx_chan;
+ struct ele_api_msg *tx_msg, *rx_msg;
+ struct completion done;
+ spinlock_t lock;
+ /*
+ * Flag to retain the state of initialization done at
+ * the time of ele-mu probe.
+ */
+ uint32_t flags;
+ u8 max_dev_ctx;
+ struct ele_mu_device_ctx **ctxs;
+ struct ele_imem_buf imem;
+};
+
+phys_addr_t get_phy_buf_mem_pool(struct device *dev,
+ char *mem_pool_name,
+ u32 **buf,
+ uint32_t size);
+void free_phybuf_mem_pool(struct device *dev,
+ char *mem_pool_name,
+ u32 *buf,
+ uint32_t size);
+#endif
diff --git a/include/linux/firmware/imx/ele_base_msg.h b/include/linux/firmware/imx/ele_base_msg.h
new file mode 100644
index 000000000000..49e3619372be
--- /dev/null
+++ b/include/linux/firmware/imx/ele_base_msg.h
@@ -0,0 +1,40 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2021-2023 NXP
+ *
+ * Header file for the ELE Base API(s).
+ */
+
+#ifndef ELE_BASE_MSG_H
+#define ELE_BASE_MSG_H
+
+#include <linux/types.h>
+
+#define WORD_SZ 4
+#define ELE_NONE_VAL 0x0
+
+#define ELE_SUCCESS_IND 0xD6
+
+#define ELE_GET_INFO_REQ 0xDA
+#define ELE_GET_INFO_REQ_MSG_SZ 0x10
+#define ELE_GET_INFO_RSP_MSG_SZ 0x08
+
+#define ELE_GET_INFO_BUFF_SZ 0x100
+#define ELE_GET_INFO_READ_SZ 0xA0
+#define DEVICE_GET_INFO_SZ 0x100
+
+#define GET_INFO_SOC_INFO_WORD_OFFSET 1
+#define GET_INFO_UUID_WORD_OFFSET 3
+#define GET_INFO_SL_NUM_MSB_WORD_OFF \
+ (GET_INFO_UUID_WORD_OFFSET + 3)
+#define GET_INFO_SL_NUM_LSB_WORD_OFF \
+ (GET_INFO_UUID_WORD_OFFSET + 0)
+
+#define ELE_PING_REQ 0x01
+#define ELE_PING_REQ_SZ 0x04
+#define ELE_PING_RSP_SZ 0x08
+
+int ele_get_info(struct device *dev, phys_addr_t addr, u32 data_size);
+int ele_ping(struct device *dev);
+
+#endif
diff --git a/include/linux/firmware/imx/ele_mu_ioctl.h b/include/linux/firmware/imx/ele_mu_ioctl.h
new file mode 100644
index 000000000000..e4017dd1337a
--- /dev/null
+++ b/include/linux/firmware/imx/ele_mu_ioctl.h
@@ -0,0 +1,74 @@
+/* SPDX-License-Identifier: (GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause*/
+/*
+ * Copyright 2019-2023 NXP
+ */
+
+#ifndef ELE_MU_IOCTL_H
+#define ELE_MU_IOCTL_H
+
+/* IOCTL definitions. */
+
+struct ele_mu_ioctl_setup_iobuf {
+ u8 *user_buf;
+ u32 length;
+ u32 flags;
+ u64 ele_addr;
+};
+
+struct ele_mu_ioctl_shared_mem_cfg {
+ u32 base_offset;
+ u32 size;
+};
+
+struct ele_mu_ioctl_get_mu_info {
+ u8 ele_mu_id;
+ u8 interrupt_idx;
+ u8 tz;
+ u8 did;
+};
+
+struct ele_mu_ioctl_signed_message {
+ u8 *message;
+ u32 msg_size;
+ u32 error_code;
+};
+
+/* IO Buffer Flags */
+#define ELE_MU_IO_FLAGS_IS_OUTPUT (0x00u)
+#define ELE_MU_IO_FLAGS_IS_INPUT (0x01u)
+#define ELE_MU_IO_FLAGS_USE_SEC_MEM (0x02u)
+#define ELE_MU_IO_FLAGS_USE_SHORT_ADDR (0x04u)
+#define ELE_MU_IO_DATA_BUF_SHE_V2X (0x08u)
+#define ELE_MU_IO_FLAGS_IS_IN_OUT (0x10u)
+
+/* IOCTLS */
+#define ELE_MU_IOCTL 0x0A /* like MISC_MAJOR. */
+
+/*
+ * ioctl to designated the current fd as logical-reciever.
+ * This is ioctl is send when the nvm-daemon, a slave to the
+ * firmware is started by the user.
+ */
+#define ELE_MU_IOCTL_ENABLE_CMD_RCV _IO(ELE_MU_IOCTL, 0x01)
+
+/*
+ * ioctl to get the buffer allocated from the memory, which is shared
+ * between kernel and FW.
+ * Post allocation, the kernel tagged the allocated memory with:
+ * Output
+ * Input
+ * Input-Output
+ * Short address
+ * Secure-memory
+ */
+#define ELE_MU_IOCTL_SETUP_IOBUF _IOWR(ELE_MU_IOCTL, 0x03, \
+ struct ele_mu_ioctl_setup_iobuf)
+
+/*
+ * ioctl to get the mu information, that is used to exchange message
+ * with FW, from user-spaced.
+ */
+#define ELE_MU_IOCTL_GET_MU_INFO _IOR(ELE_MU_IOCTL, 0x04, \
+ struct ele_mu_ioctl_get_mu_info)
+
+#endif
--
2.34.1
Enabled trng on imx93 platform through enclave fw.
Signed-off-by: Gaurav Jain <[email protected]>
Signed-off-by: Pankaj Gupta <[email protected]>
---
drivers/firmware/imx/Kconfig | 9 ++
drivers/firmware/imx/Makefile | 1 +
drivers/firmware/imx/ele_base_msg.c | 117 ++++++++++++++++++++++
drivers/firmware/imx/ele_common.c | 40 ++++++++
drivers/firmware/imx/ele_common.h | 2 +
drivers/firmware/imx/ele_fw_api.c | 67 +++++++++++++
drivers/firmware/imx/ele_fw_api.h | 6 ++
drivers/firmware/imx/ele_trng.c | 47 +++++++++
drivers/firmware/imx/se_fw.c | 21 ++++
include/linux/firmware/imx/ele_base_msg.h | 13 +++
10 files changed, 323 insertions(+)
create mode 100644 drivers/firmware/imx/ele_trng.c
diff --git a/drivers/firmware/imx/Kconfig b/drivers/firmware/imx/Kconfig
index 2822e5d4b24c..ffc02593293c 100644
--- a/drivers/firmware/imx/Kconfig
+++ b/drivers/firmware/imx/Kconfig
@@ -40,3 +40,12 @@ config IMX_SEC_ENCLAVE
like base, HSM, V2X & SHE using the SAB protocol via the shared Messaging
Unit. This driver exposes these interfaces via a set of file descriptors
allowing to configure shared memory, send and receive messages.
+
+config IMX_ELE_TRNG
+ tristate "i.MX ELE True Random Number Generator"
+ default y
+ select CRYPTO_RNG
+ select HW_RANDOM
+ help
+ This driver provides kernel-side support for the Random Number generation,
+ through NXP hardware IP for secure-enclave called EdgeLock Enclave.
diff --git a/drivers/firmware/imx/Makefile b/drivers/firmware/imx/Makefile
index d61f06a8050a..9018f7824f36 100644
--- a/drivers/firmware/imx/Makefile
+++ b/drivers/firmware/imx/Makefile
@@ -3,3 +3,4 @@ obj-$(CONFIG_IMX_DSP) += imx-dsp.o
obj-$(CONFIG_IMX_SCU) += imx-scu.o misc.o imx-scu-irq.o rm.o imx-scu-soc.o
sec_enclave-objs = se_fw.o ele_common.o ele_base_msg.o ele_fw_api.o
obj-${CONFIG_IMX_SEC_ENCLAVE} += sec_enclave.o
+sec_enclave-${CONFIG_IMX_ELE_TRNG} += ele_trng.o
diff --git a/drivers/firmware/imx/ele_base_msg.c b/drivers/firmware/imx/ele_base_msg.c
index 813f769f7bc3..3a3af2321f67 100644
--- a/drivers/firmware/imx/ele_base_msg.c
+++ b/drivers/firmware/imx/ele_base_msg.c
@@ -99,3 +99,120 @@ int ele_ping(struct device *dev)
return ret;
}
+
+/*
+ * ele_get_trng_state() - prepare and send the command to read
+ * crypto lib and TRNG state
+ * TRNG state
+ * 0x1 TRNG is in program mode
+ * 0x2 TRNG is still generating entropy
+ * 0x3 TRNG entropy is valid and ready to be read
+ * 0x4 TRNG encounter an error while generating entropy
+ *
+ * CSAL state
+ * 0x0 Crypto Lib random context initialization is not done yet
+ * 0x1 Crypto Lib random context initialization is on-going
+ * 0x2 Crypto Lib random context initialization succeed
+ * 0x3 Crypto Lib random context initialization failed
+ *
+ * returns: csal and trng state.
+ *
+ */
+int ele_get_trng_state(struct device *dev)
+{
+ struct ele_mu_priv *priv = dev_get_drvdata(dev);
+ int ret;
+ unsigned int status;
+
+ ret = imx_se_alloc_tx_rx_buf(priv);
+ if (ret)
+ return ret;
+
+ ret = plat_fill_cmd_msg_hdr(priv,
+ (struct mu_hdr *)&priv->tx_msg->header,
+ ELE_GET_TRNG_STATE_REQ,
+ ELE_GET_TRNG_STATE_REQ_MSG_SZ,
+ true);
+ if (ret) {
+ pr_err("Error: plat_fill_cmd_msg_hdr failed.\n");
+ goto exit;
+ }
+
+ ret = imx_ele_msg_send_rcv(priv);
+ if (ret)
+ goto exit;
+
+ ret = imx_ele_msg_send_rcv(priv);
+ if (ret < 0)
+ goto exit;
+
+ ret = validate_rsp_hdr(priv,
+ priv->rx_msg->header,
+ ELE_GET_TRNG_STATE_REQ,
+ ELE_GET_TRNG_STATE_RSP_MSG_SZ,
+ true);
+ if (ret)
+ goto exit;
+
+ status = RES_STATUS(priv->rx_msg->data[0]);
+ if (status != priv->success_tag) {
+ dev_err(dev, "Command Id[%d], Response Failure = 0x%x",
+ ELE_GET_TRNG_STATE_REQ, status);
+ ret = -1;
+ } else
+ ret = (priv->rx_msg->data[1] & CSAL_TRNG_STATE_MASK);
+
+exit:
+ imx_se_free_tx_rx_buf(priv);
+
+ return ret;
+}
+
+/*
+ * ele_start_rng() - prepare and send the command to start
+ * initialization of the ELE RNG context
+ *
+ * returns: 0 on success.
+ */
+int ele_start_rng(struct device *dev)
+{
+ struct ele_mu_priv *priv = dev_get_drvdata(dev);
+ int ret;
+ unsigned int status;
+
+ ret = imx_se_alloc_tx_rx_buf(priv);
+ if (ret)
+ return ret;
+
+ ret = plat_fill_cmd_msg_hdr(priv,
+ (struct mu_hdr *)&priv->tx_msg->header,
+ ELE_START_RNG_REQ,
+ ELE_START_RNG_REQ_MSG_SZ,
+ true);
+ if (ret)
+ goto exit;
+
+ ret = imx_ele_msg_send_rcv(priv);
+ if (ret < 0)
+ goto exit;
+
+ ret = validate_rsp_hdr(priv,
+ priv->rx_msg->header,
+ ELE_START_RNG_REQ,
+ ELE_START_RNG_RSP_MSG_SZ,
+ true);
+ if (ret)
+ goto exit;
+
+ status = RES_STATUS(priv->rx_msg->data[0]);
+ if (status != priv->success_tag) {
+ dev_err(dev, "Command Id[%d], Response Failure = 0x%x",
+ ELE_START_RNG_REQ, status);
+ ret = -1;
+ }
+
+exit:
+ imx_se_free_tx_rx_buf(priv);
+
+ return ret;
+}
diff --git a/drivers/firmware/imx/ele_common.c b/drivers/firmware/imx/ele_common.c
index 4410245a19ec..d4b829c19133 100644
--- a/drivers/firmware/imx/ele_common.c
+++ b/drivers/firmware/imx/ele_common.c
@@ -3,6 +3,10 @@
* Copyright 2023 NXP
*/
+#include <linux/delay.h>
+#include <linux/device.h>
+#include <linux/firmware/imx/ele_base_msg.h>
+
#include "ele_common.h"
#include "se_fw.h"
@@ -137,3 +141,39 @@ int validate_rsp_hdr(struct ele_mu_priv *priv, unsigned int header,
return ret;
}
+
+int ele_do_start_rng(struct device *dev)
+{
+ int ret;
+ int count = ELE_GET_TRNG_STATE_RETRY_COUNT;
+
+ ret = ele_get_trng_state(dev);
+ if (ret < 0) {
+ dev_err(dev, "Failed to get trng state\n");
+ return ret;
+ } else if (ret != ELE_TRNG_STATE_OK) {
+ /* call start rng */
+ ret = ele_start_rng(dev);
+ if (ret) {
+ dev_err(dev, "Failed to start rng\n");
+ return ret;
+ }
+
+ /* poll get trng state API, ELE_GET_TRNG_STATE_RETRY_COUNT times
+ * or while trng state != 0x203
+ */
+ do {
+ msleep(10);
+ ret = ele_get_trng_state(dev);
+ if (ret < 0) {
+ dev_err(dev, "Failed to get trng state\n");
+ return ret;
+ }
+ count--;
+ } while ((ret != ELE_TRNG_STATE_OK) && count);
+ if (ret != ELE_TRNG_STATE_OK)
+ return -EIO;
+ }
+
+ return 0;
+}
diff --git a/drivers/firmware/imx/ele_common.h b/drivers/firmware/imx/ele_common.h
index 284b7f66d8e3..f9e1d949dc6a 100644
--- a/drivers/firmware/imx/ele_common.h
+++ b/drivers/firmware/imx/ele_common.h
@@ -27,4 +27,6 @@ static inline int ele_trng_init(struct device *dev)
return 0;
}
#endif
+
+int ele_do_start_rng(struct device *dev);
#endif
diff --git a/drivers/firmware/imx/ele_fw_api.c b/drivers/firmware/imx/ele_fw_api.c
index 55dda9d6531a..d195a920b3ee 100644
--- a/drivers/firmware/imx/ele_fw_api.c
+++ b/drivers/firmware/imx/ele_fw_api.c
@@ -49,3 +49,70 @@ int ele_init_fw(struct device *dev)
return ret;
}
+
+/*
+ * ele_get_random() - prepare and send the command to proceed
+ * with a random number generation operation
+ *
+ * returns: size of the rondom number generated
+ */
+int ele_get_random(struct device *dev,
+ void *data, size_t len)
+{
+ struct ele_mu_priv *priv = dev_get_drvdata(dev);
+ unsigned int status;
+ dma_addr_t dst_dma;
+ u8 *buf;
+ int ret;
+
+ buf = dmam_alloc_coherent(priv->dev, len, &dst_dma, GFP_KERNEL);
+ if (!buf) {
+ dev_err(priv->dev, "Failed to map destination buffer memory\n");
+ return -ENOMEM;
+ }
+
+ ret = imx_se_alloc_tx_rx_buf(priv);
+ if (ret) {
+ ret = -ENOMEM;
+ goto exit1;
+ }
+
+ ret = plat_fill_cmd_msg_hdr(priv,
+ (struct mu_hdr *)&priv->tx_msg->header,
+ ELE_GET_RANDOM_REQ, ELE_GET_RANDOM_REQ_SZ,
+ false);
+ if (ret)
+ goto exit;
+
+ priv->tx_msg->data[0] = 0x0;
+ priv->tx_msg->data[1] = dst_dma;
+ priv->tx_msg->data[2] = len;
+ ret = imx_ele_msg_send_rcv(priv);
+ if (ret < 0)
+ goto exit;
+
+ ret = validate_rsp_hdr(priv,
+ priv->rx_msg->header,
+ ELE_GET_RANDOM_REQ,
+ ELE_GET_RANDOM_RSP_SZ,
+ false);
+ if (ret)
+ return ret;
+
+ status = RES_STATUS(priv->rx_msg->data[0]);
+ if (status != priv->success_tag) {
+ dev_err(dev, "Command Id[%d], Response Failure = 0x%x",
+ ELE_GET_RANDOM_REQ, status);
+ ret = -1;
+ } else {
+ memcpy(data, buf, len);
+ ret = len;
+ }
+
+exit:
+ imx_se_free_tx_rx_buf(priv);
+exit1:
+ dmam_free_coherent(priv->dev, len, buf, dst_dma);
+
+ return ret;
+}
diff --git a/drivers/firmware/imx/ele_fw_api.h b/drivers/firmware/imx/ele_fw_api.h
index 21bb35b4041f..70cd8cf5074b 100644
--- a/drivers/firmware/imx/ele_fw_api.h
+++ b/drivers/firmware/imx/ele_fw_api.h
@@ -14,7 +14,13 @@
#define ELE_INIT_FW_REQ_SZ 0x04
#define ELE_INIT_FW_RSP_SZ 0x08
+#define ELE_GET_RANDOM_REQ 0xCD
+#define ELE_GET_RANDOM_REQ_SZ 0x10
+#define ELE_GET_RANDOM_RSP_SZ 0x08
+
int ele_init_fw(struct device *dev);
+int ele_get_random(struct device *dev, void *data, size_t len);
+int ele_get_hwrng(struct hwrng *rng, void *data, size_t len, bool wait);
#endif /* ELE_FW_API_H */
diff --git a/drivers/firmware/imx/ele_trng.c b/drivers/firmware/imx/ele_trng.c
new file mode 100644
index 000000000000..4a7a119ff435
--- /dev/null
+++ b/drivers/firmware/imx/ele_trng.c
@@ -0,0 +1,47 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * ELE Random Number Generator Driver NXP's Platforms
+ *
+ * Copyright 2023 NXP
+ */
+
+#include "ele_common.h"
+#include "ele_fw_api.h"
+
+struct ele_trng {
+ struct hwrng rng;
+ struct device *dev;
+};
+
+int ele_trng_init(struct device *dev)
+{
+ struct ele_trng *trng;
+ int ret;
+
+ trng = devm_kzalloc(dev, sizeof(*trng), GFP_KERNEL);
+ if (!trng)
+ return -ENOMEM;
+
+ trng->dev = dev;
+ trng->rng.name = "ele-trng";
+ trng->rng.read = ele_get_hwrng;
+ trng->rng.priv = (unsigned long)trng;
+ trng->rng.quality = 1024;
+
+ dev_dbg(dev, "registering ele-trng\n");
+
+ ret = devm_hwrng_register(dev, &trng->rng);
+ if (ret)
+ return ret;
+
+ dev_info(dev, "Successfully registered ele-trng\n");
+ return 0;
+}
+
+int ele_get_hwrng(struct hwrng *rng,
+ void *data, size_t len, bool wait)
+{
+ struct ele_trng *trng = (struct ele_trng *)rng->priv;
+
+ return ele_get_random(trng->dev, data, len);
+}
diff --git a/drivers/firmware/imx/se_fw.c b/drivers/firmware/imx/se_fw.c
index 92dc8ea58960..3638a4fed5e7 100644
--- a/drivers/firmware/imx/se_fw.c
+++ b/drivers/firmware/imx/se_fw.c
@@ -24,6 +24,7 @@
#include <linux/sys_soc.h>
#include "se_fw.h"
+#include "ele_common.h"
#include "ele_fw_api.h"
#define SOC_ID_OF_IMX8ULP 0x084D
@@ -48,6 +49,9 @@ struct imx_info {
uint8_t *pool_name;
bool reserved_dma_ranges;
bool init_fw;
+ /* platform specific flag to enable/disable the ELE True RNG */
+ bool start_rng;
+ bool enable_ele_trng;
};
struct imx_info_list {
@@ -76,6 +80,8 @@ static const struct imx_info_list imx8ulp_info = {
.pool_name = "sram",
.reserved_dma_ranges = true,
.init_fw = false,
+ .start_rng = true,
+ .enable_ele_trng = false,
},
},
};
@@ -99,6 +105,8 @@ static const struct imx_info_list imx93_info = {
.pool_name = NULL,
.reserved_dma_ranges = true,
.init_fw = true,
+ .start_rng = true,
+ .enable_ele_trng = true,
},
},
};
@@ -1260,6 +1268,19 @@ static int se_fw_probe(struct platform_device *pdev)
if (ret)
dev_err(dev, "Failed[%d] to ping the fw.\n", ret);
+ /* start ele rng */
+ if (info->start_rng) {
+ ret = ele_do_start_rng(dev);
+ if (ret)
+ dev_err(dev, "Failed to start ele rng\n");
+ }
+
+ if (!ret && info->enable_ele_trng) {
+ ret = ele_trng_init(dev);
+ if (ret)
+ dev_err(dev, "Failed to init ele-trng\n");
+ }
+
dev_info(dev, "i.MX secure-enclave: %s interface to firmware, configured.\n",
info->pdev_name[1]);
diff --git a/include/linux/firmware/imx/ele_base_msg.h b/include/linux/firmware/imx/ele_base_msg.h
index 49e3619372be..3ca4b47e4c4e 100644
--- a/include/linux/firmware/imx/ele_base_msg.h
+++ b/include/linux/firmware/imx/ele_base_msg.h
@@ -34,7 +34,20 @@
#define ELE_PING_REQ_SZ 0x04
#define ELE_PING_RSP_SZ 0x08
+#define ELE_START_RNG_REQ 0xA3
+#define ELE_START_RNG_REQ_MSG_SZ 0x04
+#define ELE_START_RNG_RSP_MSG_SZ 0x08
+
+#define ELE_GET_TRNG_STATE_REQ 0xA4
+#define ELE_GET_TRNG_STATE_REQ_MSG_SZ 0x04
+#define ELE_GET_TRNG_STATE_RSP_MSG_SZ 0x0C
+#define ELE_TRNG_STATE_OK 0x203
+#define ELE_GET_TRNG_STATE_RETRY_COUNT 0x5
+#define CSAL_TRNG_STATE_MASK 0x0000ffff
+
int ele_get_info(struct device *dev, phys_addr_t addr, u32 data_size);
int ele_ping(struct device *dev);
+int ele_start_rng(struct device *dev);
+int ele_get_trng_state(struct device *dev);
#endif
--
2.34.1
On Mon, 30 Oct 2023 15:28:40 +0530, Pankaj Gupta wrote:
> The NXP's i.MX EdgeLock Enclave, a HW IP creating an embedded
> secure enclave within the SoC boundary to enable features like
> - HSM
> - SHE
> - V2X
>
> Communicates via message unit with linux kernel. This driver
> is enables communication ensuring well defined message sequence
> protocol between Application Core and enclave's firmware.
>
> Driver configures multiple misc-device on the MU, for multiple
> user-space applications can communicate on single MU.
>
> It exists on some i.MX processors. e.g. i.MX8ULP, i.MX93 etc.
>
> Signed-off-by: Pankaj Gupta <[email protected]>
> ---
> .../bindings/firmware/fsl,imx-se-fw.yaml | 83 +++++++++++++++++++
> 1 file changed, 83 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/firmware/fsl,imx-se-fw.yaml
>
My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):
yamllint warnings/errors:
dtschema/dtc warnings/errors:
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/dma/stericsson,dma40.example.dtb: dma-controller@801c0000: sram:0: [4294967295, 4294967295] is too long
from schema $id: http://devicetree.org/schemas/dma/stericsson,dma40.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/firmware/fsl,imx-se-fw.example.dtb: se-fw2: 'memory-region' is a required property
from schema $id: http://devicetree.org/schemas/firmware/fsl,imx-se-fw.yaml#
doc reference errors (make refcheckdocs):
See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/[email protected]
The base for the series is generally the latest rc1. A different dependency
should be noted in *this* patch.
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:
pip3 install dtschema --upgrade
Please check and re-submit after running the above command yourself. Note
that DT_SCHEMA_FILES can be set to your schema file to speed up checking
your schema. However, it must be unset to test all examples with your schema.
On 30/10/2023 10:58, Pankaj Gupta wrote:
> The NXP's i.MX EdgeLock Enclave, a HW IP creating an embedded
> secure enclave within the SoC boundary to enable features like
> - HSM
> - SHE
> - V2X
>
> Communicates via message unit with linux kernel. This driver
> is enables communication ensuring well defined message sequence
> protocol between Application Core and enclave's firmware.
>
> Driver configures multiple misc-device on the MU, for multiple
> user-space applications can communicate on single MU.
>
> It exists on some i.MX processors. e.g. i.MX8ULP, i.MX93 etc.
>
> Signed-off-by: Pankaj Gupta <[email protected]>
> ---
> .../bindings/firmware/fsl,imx-se-fw.yaml | 83 +++++++++++++++++++
> 1 file changed, 83 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/firmware/fsl,imx-se-fw.yaml
>
> diff --git a/Documentation/devicetree/bindings/firmware/fsl,imx-se-fw.yaml b/Documentation/devicetree/bindings/firmware/fsl,imx-se-fw.yaml
> new file mode 100644
> index 000000000000..0503ea497d61
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/firmware/fsl,imx-se-fw.yaml
> @@ -0,0 +1,83 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/firmware/fsl,imx-se-fw.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: NXP i.MX EdgeLock Enclave Firmware (ELEFW)
> +
> +maintainers:
> + - Pankaj Gupta <[email protected]>
> +
> +description:
This is a friendly reminder during the review process.
It seems my or other reviewer's previous comments were not fully
addressed. Maybe the feedback got lost between the quotes, maybe you
just forgot to apply it. Please go back to the previous discussion and
either implement all requested changes or keep discussing them.
Thank you.
Also - not tested
> + The NXP's i.MX EdgeLock Enclave, a HW IP creating an embedded
> + secure enclave within the SoC boundary to enable features like
> + - HSM
> + - SHE
> + - V2X
> +
> + It uses message unit to communicate and coordinate to pass messages
> + (e.g., data, status and control) through its interfaces.
> +
> +properties:
> + compatible:
> + enum:
> + - fsl,imx8ulp-se-fw
> + - fsl,imx93-se-fw
> +
> + mboxes:
> + description:
> + All MU channels must be within the same MU instance. Cross instances are
> + not allowed. Users need to ensure that used MU instance does not conflict
> + with other execution environments.
> + items:
> + - description: TX0 MU channel
> + - description: RX0 MU channel
> +
> + mbox-names:
> + items:
> + - const: tx
> + - const: rx
> +
> + memory-region:
> + items:
> + - description: Reserved memory region that can be accessed by firmware. Used for
> + exchanging the buffers between driver and firmware.
> +
> + sram:
> + description: Phandle to the device SRAM
Nothing improved
> + $ref: /schemas/types.yaml#/definitions/phandle-array
How many items? What's inside?
> +
> +required:
> + - compatible
> + - mboxes
> + - mbox-names
> +
> +allOf:
> + # memory-region
> + - if:
> + properties:
> + compatible:
> + contains:
> + enum:
> + - fsl,imx8ulp-se-fw
> + - fsl,imx93-se-fw
> + then:
> + required:
> + - memory-region
> + else:
> + not:
> + required:
> + - memory-region
That's not the syntax. Test it.
You wanted :false
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + se-fw2 {
And how suddenly "2" appeared here? Anyway:
Node names should be generic. See also an explanation and list of
examples (not exhaustive) in DT specification:
https://devicetree-specification.readthedocs.io/en/latest/chapter2-devicetree-basics.html#generic-names-recommendation
> + compatible = "fsl,imx8ulp-se-fw";
> + mbox-names = "tx", "rx";
> + mboxes = <&s4muap 0 0>, <&s4muap 1 0>;
Add complete example, so you miss sram.
This code is not going well. :( I understand some discussions on
properties but lack of testing? At v7 of patchset still not tested?
Best regards,
Krzysztof
On 30/10/2023 10:58, Pankaj Gupta wrote:
> Added support for NXP secure enclave called EdgeLock Enclave
> firmware (se-fw) for imx8ulp-evk.
>
> Signed-off-by: Pankaj Gupta <[email protected]>
> ---
> arch/arm64/boot/dts/freescale/imx8ulp.dtsi | 10 +++++++++-
> 1 file changed, 9 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi
> index 946f2b68d16f..7b66de3a392d 100644
> --- a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi
> @@ -152,7 +152,7 @@ sosc: clock-sosc {
> #clock-cells = <0>;
> };
>
> - sram@2201f000 {
> + sram0: sram@2201f000 {
> compatible = "mmio-sram";
> reg = <0x0 0x2201f000 0x0 0x1000>;
>
> @@ -578,4 +578,12 @@ gpiod: gpio@2e200080 {
> gpio-ranges = <&iomuxc1 0 0 24>;
> };
> };
> +
> + ele_fw2: se-fw2 {
Node names should be generic. See also an explanation and list of
examples (not exhaustive) in DT specification:
https://devicetree-specification.readthedocs.io/en/latest/chapter2-devicetree-basics.html#generic-names-recommendation
Best regards,
Krzysztof
On 30/10/2023 10:58, Pankaj Gupta wrote:
> Added support for NXP secure enclave called EdgeLock Enclave
> firmware (se-fw) for imx93-11x11-evk.
>
> Signed-off-by: Pankaj Gupta <[email protected]>
> ---
> arch/arm64/boot/dts/freescale/imx93.dtsi | 8 +++++++-
> 1 file changed, 7 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx93.dtsi b/arch/arm64/boot/dts/freescale/imx93.dtsi
> index dcf6e4846ac9..197de680fd27 100644
> --- a/arch/arm64/boot/dts/freescale/imx93.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx93.dtsi
> @@ -1,6 +1,6 @@
> // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> /*
> - * Copyright 2022 NXP
> + * Copyright 2022-2023 NXP
> */
>
> #include <dt-bindings/clock/imx93-clock.h>
> @@ -925,4 +925,10 @@ ddr-pmu@4e300dc0 {
> interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
> };
> };
> +
> + ele_fw2: se-fw2 {
Node names should be generic. See also an explanation and list of
examples (not exhaustive) in DT specification:
https://devicetree-specification.readthedocs.io/en/latest/chapter2-devicetree-basics.html#generic-names-recommendation
Why do you even need label?
Best regards,
Krzysztof
On 30/10/2023 10:58, Pankaj Gupta wrote:
> EdgeLock Enclave are has a hardware limitation of restricted access
> to the DDR memory range:
> - 0x80000000 0x9FFFFFFF
>
> ELE-MU driver requireis 1MB of memory. In this patch, reserving
> 1MB of ddr memory region from the lower 32-bit range.
>
> Signed-off-by: Dong Aisheng <[email protected]>
> Signed-off-by: Pankaj Gupta <[email protected]>
> ---
> arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts | 15 +++++++++++++++
> 1 file changed, 15 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts b/arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts
> index cafd39130eb8..bcb4ae931c64 100644
> --- a/arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts
> +++ b/arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts
> @@ -7,6 +7,10 @@
>
> #include "imx93.dtsi"
>
> +&ele_fw2 {
OK, this explains the label in imx93.dtsi, but then node in the
imx93.dtsi is incomplete and should be disabled. Everything which is
incomplete should be disabled in DTSI by default. At v7 of your patchset
I really would expect some internal review happening.
> + memory-region = <&ele_reserved>;
> +};
> +
> / {
> model = "NXP i.MX93 11X11 EVK board";
> compatible = "fsl,imx93-11x11-evk", "fsl,imx93";
> @@ -68,6 +72,17 @@ reg_vref_1v8: regulator-adc-vref {
> regulator-max-microvolt = <1800000>;
> };
>
> + reserved-memory {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> + ele_reserved: ele-reserved@a4120000 {
Names in reserved memory should match the purpose, so "reserved" is here
redundant. Just "ele".
> + compatible = "shared-dma-pool";
> + reg = <0 0xa4120000 0 0x100000>;
> + no-map;
> + };
> + };
> +
> reg_usdhc2_vmmc: regulator-usdhc2 {
> compatible = "regulator-fixed";
> pinctrl-names = "default";
Best regards,
Krzysztof
On 30/10/2023 10:58, Pankaj Gupta wrote:
> Documented i.MX SoC's Service layer and C_DEV driver for SoC(s)
> enabled with hardware IP for secure-enclaves like:
> - edgelock enclave on i.MX93 & i.MX8ULP
>
> Signed-off-by: Pankaj Gupta <[email protected]>
I asked to explain user-space tools as well. I don't see them
mentioned/documented in none of the commits.
Best regards,
Krzysztof
On 30/10/2023 18:57, Krzysztof Kozlowski wrote:
> On 30/10/2023 10:58, Pankaj Gupta wrote:
>> Documented i.MX SoC's Service layer and C_DEV driver for SoC(s)
>> enabled with hardware IP for secure-enclaves like:
>> - edgelock enclave on i.MX93 & i.MX8ULP
>>
>> Signed-off-by: Pankaj Gupta <[email protected]>
>
> I asked to explain user-space tools as well. I don't see them
> mentioned/documented in none of the commits.
Hm, I lost somehow or I did not get your patch #7, so maybe that's the
place where they are mentioned.
Best regards,
Krzysztof
On 30/10/2023 10:58, Pankaj Gupta wrote:
> The Edgelock Enclave , is the secure enclave embedded in the SoC
> to support the features like HSM, SHE & V2X, using message based
> communication channel.
>
> ELE FW communicates on a dedicated MU with application core where
> kernel is running. It exists on specific i.MX processors. e.g.
> i.MX8ULP, i.MX93.
>
> User-space library using this driver:
> - i.MX Secure Enclave library:
> -- URL: https://github.com/nxp-imx/imx-secure-enclave.git,
> - i.MX Secure Middle-Ware:
> -- URL: https://github.com/nxp-imx/imx-smw.git
OK, I got your patch #7. Thanks for documenting the user-space.
>
> Signed-off-by: Pankaj Gupta <[email protected]>
...
> diff --git a/drivers/firmware/imx/ele_common.c b/drivers/firmware/imx/ele_common.c
> new file mode 100644
> index 000000000000..4410245a19ec
> --- /dev/null
> +++ b/drivers/firmware/imx/ele_common.c
> @@ -0,0 +1,139 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright 2023 NXP
> + */
> +
> +#include "ele_common.h"
> +#include "se_fw.h"
> +
> +int imx_se_alloc_tx_rx_buf(struct ele_mu_priv *priv)
> +{
> + int ret = 0;
> +
> + priv->tx_msg = devm_kzalloc(priv->dev,
> + sizeof(*priv->tx_msg),
> + GFP_KERNEL);
> + if (!priv->tx_msg) {
> + ret = -ENOMEM;
> + dev_err(priv->dev, "Fail allocate mem for tx_msg.\n");
No improvements. I assume rest of feedback could still be ignored. I am
not going to check. It's your duty to implement the comments, not mine
to check every line whether you did it or not. Trust does not work like
that.
Best regards,
Krzysztof
Hi all,
We took a step back.
We are doing internal review ongoing on this patch-set.
Thanks everybody helping me improving the patch series.
Thanks. Krzysztof for your guidance for the entire patch-set.
Regards
Pankaj
> -----Original Message-----
> From: Pankaj Gupta <[email protected]>
> Sent: Monday, October 30, 2023 3:29 PM
> To: [email protected]; [email protected];
> [email protected]; [email protected]; [email protected];
> [email protected]; [email protected]; dl-linux-imx <linux-
> [email protected]>; [email protected]; [email protected];
> [email protected]; [email protected];
> [email protected]; [email protected]; Gaurav Jain
> <[email protected]>; [email protected]; Varun Sethi
> <[email protected]>
> Cc: Pankaj Gupta <[email protected]>
> Subject: [PATCH v7 00/11] firmware: imx: NXP Secure-Enclave FW Driver
>
> V7 Changes:
> - 2/11 DT Binding: Disposed off comments from .yaml
> -- added | to preserve formating.
> -- removed extra spaces, restricting under 80 col.
> -- replaced the "fsl,sram" property, with standard property "sram".
> -- Added details about usage of sram.
> -- removed the property "mu_id".
> -- Added allOf:if:then: for reserved memory.
> -- removed label.
>
> - 3,4,5,6/11: DTSI changes:
> -- removed the property "mu_id".
> -- rename node-name & label
>
> - 7/11 firmware: imx: add driver for NXP EdgeLock Enclave:
> -- Removed dev_err for the cases of failure in memory allocation.
> -- For others, coverted dev_err to dev_dbg.
> -- Updated the commit msg about the details for userspace lib
>
>
> V6 Changes:
>
> - 1/11 (New): Kernel doc: "Documentation/driver-
> api/firmware/other_interfaces.rst" is added.
>
> - 2/11 DT Binding: Disposed off comments from .yaml
> -- replaced the "sram-pool" property, with standard property
> "fsl,sram".
> -- removed the additional details from the description.
>
> - 3,4,5,6/11: DTSI changes:
> -- Validated using the following commands:
> --- make dt_binding_check DT_SCHEMA_FILES=freescale
> --- make CHECK_DTBS=y freescale/imx8ulp-evk.dtb;
> make CHECK_DTBS=y freescale/imx93-11x11-evk.dtb
>
> - 7/11 firmware: imx: add driver for NXP EdgeLock Enclave:
> -- Removed:
> Reported-by: kernel test robot <[email protected]>
> Closes:https://lore.kernel.org/oe-kbuild-
> all/[email protected]
> -- pr_info is removed.
> -- macro "devctx_info", "devctx_dbg" & "devctx_err" is removed.
> -- Updated ABI:
> --- Users: user-space SE-LIB, crypto-api, imx-ocotp-ele driver , smw
> --- IOCTLS: Updated the ioctl
> --- read/write:
> -- Correct message header validation.
> --- segregated handling of the error, while msg header parsing.
> -- removed TX and RX messages static allocation in state container.
> -- ran coccicheck: make C=1 CHECK=scripts/coccicheck
> drivers/firmware/imx/*.* W=1
> --- ran on all the patches.
> - 8/11 firmware: imx: init-fw api exchange on imx93
> -- removed TX and RX messages static allocation in state container.
> -- moved the header file ele_fw_api.h, to driver/firmware/imx/
> -- segregated handling of the error, while msg header parsing.
>
> - 9/11 firmware: imx: enable trng
> -- macro "devctx_info", "devctx_dbg" & "devctx_err" is removed.
> -- will remove this patch, will send this patch later, including RNG and
> crypto-maintainers.
>
>
>
>
> - 10/11 firmware: imx: enclave-fw: add handling for save/restore IMEM region
> -- Linux comment style fixed.
>
> - 10/11(old)(Removed) firmware: imx: enclave api to read-common-fuses
> -- This API will be used by imx-ocotp-ele.c.
> -- This patch can be sent later, when the changes to imx-ocotp-ele.c
> will be sent.
> -- "Documentation/driver-api/firmware/other_interfaces.rst" will be
> update for the exported symbols:
> - read_common_fuses()
> - get_se_dev()
>
> v5 Changes:
> - 1/7 DT Binding: Disposed off comments from .yaml
> -- to use "-", instead of "_".
> -- to use generic name, concatinated with soc-id.
> -- removed mu-did.
> -- renamed the ele-mu to se-fw
> -- moved the file from .../arm/freescale/ to .../firmware/
> - 2/7 Changed the .dtsi, as per the comments.
> -- removed mu-did
> -- renamed the ele_mu to se-fw.
> -- updated the compatible string.
> -- tested the DTB.
> - 4/7 Changed the .dtsi, as per the comments.
> -- removed mu-did
> -- renamed the ele_mu to se-fw.
> -- updated the compatible string.
> -- tested the DTB.
> - 6/7 Changes in driver code:
> -- replace pr_err with dev_err
> -- removed export symbols, except one, which will be used in other
> driver.
> -- Each API, send-recived based on device reference.
> -- Divided the commits into smaller commits.
> - Base Driver
> -- Added ABI file.
> - 7/11 (new) firmware: imx: init-fw api exchange on imx93
> - 8/11 (new) firmware: imx: enable trng
> - 9/11 (new) firmware: imx: enclave-fw: add handling for
> save/restore IMEM region
> - 10/11 (new) firmware: imx: enclave api to read-common-
> fuses
>
> v4 Changes:
> - Post internal review, changed the name from "ele-mu" to "se-fw".
> - Disposed-off comments in the dt-binding file.
> - Removed the non-hw related dt-bindings from the driver code.
> - Corrected the File MAINTAINERS for correct name of yaml file.
>
> v3 Changes:
> - update the commit message for documentation.
> - Fixed dt-binding checking error for file- fsl,ele_mu.yaml
> - Coverity fixes in the ele_mu.c
>
> v2 Changes:
> - Fixed Kernel Test Bot issues.
> - Removed ".../devicetree/bindings/mailbox/fsl,muap.txt"
>
> The NXP's i.MX EdgeLock Enclave, a HW IP creating an embedded secure
> enclave within the SoC boundary to enable features like
> - HSM
> - SHE
> - V2X
>
> Communicates via message unit with linux kernel. This driver is enables
> communication ensuring well defined message sequence protocol between
> Application Core and enclave's firmware.
>
> Driver configures multiple misc-device on the MU, for multiple user-space
> applications can communicate on single MU.
>
> It exists on some i.MX processors. e.g. i.MX8ULP, i.MX93 etc.
>
> Pankaj Gupta (11):
> Documentation/firmware: added imx/se-fw to other_interfaces
> dt-bindings: arm: fsl: add imx-se-fw binding doc
> arm64: dts: imx8ulp-evk: added nxp secure enclave firmware
> arm64: dts: imx8ulp-evk: reserved mem-ranges to constrain ele_fw
> dma-range
> arm64: dts: imx93-11x11-evk: added nxp secure enclave fw
> arm64: dts: imx93-11x11-evk: reserved mem-ranges
> firmware: imx: add driver for NXP EdgeLock Enclave
> firmware: imx: init-fw api exchange on imx93
> firmware: imx: enable trng
> firmware: imx: enclave-fw: add handling for save/restore IMEM region
> MAINTAINERS: Added maintainer details
>
> Documentation/ABI/testing/se-cdev | 41 +
> .../bindings/firmware/fsl,imx-se-fw.yaml | 83 +
> .../driver-api/firmware/other_interfaces.rst | 67 +
> MAINTAINERS | 10 +
> arch/arm64/boot/dts/freescale/imx8ulp-evk.dts | 15 +
> arch/arm64/boot/dts/freescale/imx8ulp.dtsi | 10 +-
> .../boot/dts/freescale/imx93-11x11-evk.dts | 15 +
> arch/arm64/boot/dts/freescale/imx93.dtsi | 8 +-
> drivers/firmware/imx/Kconfig | 21 +
> drivers/firmware/imx/Makefile | 3 +
> drivers/firmware/imx/ele_base_msg.c | 271 ++++
> drivers/firmware/imx/ele_common.c | 294 ++++
> drivers/firmware/imx/ele_common.h | 40 +
> drivers/firmware/imx/ele_fw_api.c | 118 ++
> drivers/firmware/imx/ele_fw_api.h | 26 +
> drivers/firmware/imx/ele_trng.c | 47 +
> drivers/firmware/imx/se_fw.c | 1376 +++++++++++++++++
> drivers/firmware/imx/se_fw.h | 154 ++
> include/linux/firmware/imx/ele_base_msg.h | 67 +
> include/linux/firmware/imx/ele_mu_ioctl.h | 74 +
> 20 files changed, 2738 insertions(+), 2 deletions(-) create mode 100644
> Documentation/ABI/testing/se-cdev create mode 100644
> Documentation/devicetree/bindings/firmware/fsl,imx-se-fw.yaml
> create mode 100644 drivers/firmware/imx/ele_base_msg.c
> create mode 100644 drivers/firmware/imx/ele_common.c create mode
> 100644 drivers/firmware/imx/ele_common.h create mode 100644
> drivers/firmware/imx/ele_fw_api.c create mode 100644
> drivers/firmware/imx/ele_fw_api.h create mode 100644
> drivers/firmware/imx/ele_trng.c create mode 100644
> drivers/firmware/imx/se_fw.c create mode 100644
> drivers/firmware/imx/se_fw.h create mode 100644
> include/linux/firmware/imx/ele_base_msg.h
> create mode 100644 include/linux/firmware/imx/ele_mu_ioctl.h
>
> --
> 2.34.1
>