Add an entry for the Svadu extension to the riscv,isa-extensions property.
Signed-off-by: Yong-Xuan Wang <[email protected]>
Acked-by: Conor Dooley <[email protected]>
Reviewed-by: Andrew Jones <[email protected]>
---
Documentation/devicetree/bindings/riscv/extensions.yaml | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml
index cc1f546fdbdc..b5a0aed0165b 100644
--- a/Documentation/devicetree/bindings/riscv/extensions.yaml
+++ b/Documentation/devicetree/bindings/riscv/extensions.yaml
@@ -147,6 +147,12 @@ properties:
ratified at commit 3f9ed34 ("Add ability to manually trigger
workflow. (#2)") of riscv-time-compare.
+ - const: svadu
+ description: |
+ The standard Svadu supervisor-level extension for hardware updating
+ of PTE A/D bits as frozen at commit b65e07c ("move to Frozen
+ state") of riscv-svadu.
+
- const: svinval
description:
The standard Svinval supervisor-level extension for fine-grained
--
2.17.1