The MT8173 infracfg clock driver does initialization in two steps, via a
CLK_OF_DECLARE_DRIVER declaration. However its early init function
doesn't get to run when it's built as a module, presumably since it's
not loaded by the time it would have been called by of_clk_init(). This
causes its second-step probe() to return -ENOMEM when trying to register
clocks, as the necessary clock_data struct isn't initialized by the
first step.
MT2701 and MT6797 clock drivers also use this mechanism, but they try to
allocate the necessary clock_data structure if missing in the second
step. Mimic that for the MT8173 infracfg clock as well to make it work
as a module.
Signed-off-by: Alper Nebi Yasak <[email protected]>
---
Changes in v2:
- Rewrite patch subject for consistency
v1: https://lore.kernel.org/lkml/[email protected]/
drivers/clk/mediatek/clk-mt8173-infracfg.c | 12 +++++++++++-
1 file changed, 11 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/mediatek/clk-mt8173-infracfg.c b/drivers/clk/mediatek/clk-mt8173-infracfg.c
index 2f2f074e231a..ecc8b0063ea5 100644
--- a/drivers/clk/mediatek/clk-mt8173-infracfg.c
+++ b/drivers/clk/mediatek/clk-mt8173-infracfg.c
@@ -98,7 +98,17 @@ CLK_OF_DECLARE_DRIVER(mtk_infrasys, "mediatek,mt8173-infracfg",
static int clk_mt8173_infracfg_probe(struct platform_device *pdev)
{
struct device_node *node = pdev->dev.of_node;
- int r;
+ int r, i;
+
+ if (!infra_clk_data) {
+ infra_clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK);
+ if (!infra_clk_data)
+ return -ENOMEM;
+ } else {
+ for (i = 0; i < CLK_INFRA_NR_CLK; i++)
+ if (infra_clk_data->hws[i] == ERR_PTR(-EPROBE_DEFER))
+ infra_clk_data->hws[i] = ERR_PTR(-ENOENT);
+ }
r = mtk_clk_register_gates(&pdev->dev, node, infra_gates,
ARRAY_SIZE(infra_gates), infra_clk_data);
base-commit: bc962b35b139dd52319e6fc0f4bab00593bf38c9
--
2.42.0
A previous patch fixes an issue with the mt8173-infracfg clock driver
when working as a module, but has the side effect of skipping set up of
CLK_INFRA_CLK_13M in that case. This clock is used by the timer device.
Similar to the MT8183, MT8192, MT8195 and MT8186 cases [1], change the
input clock of the timer block a fixed factor divide-by-2 clock that
takes the 26 MHz oscillator as its input.
Also remove the RTC clock from the timer node while we're here. According
to commit 59311b19d7f63 ("clocksource/drivers/timer-mediatek: Add system
timer bindings") it is no longer used.
[1] https://lore.kernel.org/all/[email protected]/
Signed-off-by: Alper Nebi Yasak <[email protected]>
---
Tested on a MT8173 Chromebook. But I'm not sure I understand all of
this, so review with a pinch of salt.
Do we need to remove CLK_INFRA_CLK_13M from mt8173-infracfg after this?
Changes in v2:
- Add this patch
arch/arm64/boot/dts/mediatek/mt8173.dtsi | 12 ++++++++++--
1 file changed, 10 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
index c47d7d900f28..9062ca124d69 100644
--- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
@@ -244,6 +244,15 @@ psci {
cpu_on = <0x84000003>;
};
+ clk13m: fixed-factor-clock-13m {
+ compatible = "fixed-factor-clock";
+ #clock-cells = <0>;
+ clocks = <&clk26m>;
+ clock-div = <2>;
+ clock-mult = <1>;
+ clock-output-names = "clk13m";
+ };
+
clk26m: oscillator0 {
compatible = "fixed-clock";
#clock-cells = <0>;
@@ -530,8 +539,7 @@ timer: timer@10008000 {
"mediatek,mt6577-timer";
reg = <0 0x10008000 0 0x1000>;
interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_LOW>;
- clocks = <&infracfg CLK_INFRA_CLK_13M>,
- <&topckgen CLK_TOP_RTC_SEL>;
+ clocks = <&clk13m>;
};
pwrap: pwrap@1000d000 {
--
2.42.0