Hi,
Changes in v5:
- Rebased on 6.7-rc1.
- Collected the Ack tag.
Changes in v4:
- Reordered the interconnect to keep it in sorted order in patch 1/3.
Changes in v3:
- Using macro QCOM_ICC_TAG_ALWAYS instead of 0 in interconnects properties.
- Collected reviewed by tag.
Changes in v2:
- Updated the commit subject of patch 2/3.
This series adds devicetree nodes to support interconnects and usb for sdx75.
This is based on previously sent driver series[1], [2].
[1] https://lore.kernel.org/all/[email protected]/
[2] https://lore.kernel.org/all/[email protected]/
Thanks,
Rohit.
Rohit Agarwal (3):
arm64: dts: qcom: Add interconnect nodes for SDX75
arm64: dts: qcom: Add USB3 and PHY support on SDX75
arm64: dts: qcom: sdx75-idp: Enable USB3 and PHY support
arch/arm64/boot/dts/qcom/sdx75-idp.dts | 29 +++++
arch/arm64/boot/dts/qcom/sdx75.dtsi | 170 +++++++++++++++++++++++++
2 files changed, 199 insertions(+)
--
2.25.1
Add devicetree nodes for enabling USB3 controller, Qcom QMP PHY and
HS PHY on SDX75.
Signed-off-by: Rohit Agarwal <[email protected]>
Acked-by: Konrad Dybcio <[email protected]>
---
arch/arm64/boot/dts/qcom/sdx75.dtsi | 118 ++++++++++++++++++++++++++++
1 file changed, 118 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sdx75.dtsi b/arch/arm64/boot/dts/qcom/sdx75.dtsi
index b4723faf8655..7dbdf8ca6de6 100644
--- a/arch/arm64/boot/dts/qcom/sdx75.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdx75.dtsi
@@ -477,6 +477,47 @@ &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
};
};
+ usb_hsphy: phy@ff4000 {
+ compatible = "qcom,sdx75-snps-eusb2-phy", "qcom,sm8550-snps-eusb2-phy";
+ reg = <0x0 0x00ff4000 0x0 0x154>;
+ #phy-cells = <0>;
+
+ clocks = <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "ref";
+
+ resets = <&gcc GCC_QUSB2PHY_BCR>;
+
+ status = "disabled";
+ };
+
+ usb_qmpphy: phy@ff6000 {
+ compatible = "qcom,sdx75-qmp-usb3-uni-phy";
+ reg = <0x0 0x00ff6000 0x0 0x2000>;
+
+ clocks = <&gcc GCC_USB3_PHY_AUX_CLK>,
+ <&gcc GCC_USB2_CLKREF_EN>,
+ <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
+ <&gcc GCC_USB3_PHY_PIPE_CLK>;
+ clock-names = "aux",
+ "ref",
+ "cfg_ahb",
+ "pipe";
+
+ power-domains = <&gcc GCC_USB3_PHY_GDSC>;
+
+ resets = <&gcc GCC_USB3_PHY_BCR>,
+ <&gcc GCC_USB3PHY_PHY_BCR>;
+ reset-names = "phy",
+ "phy_phy";
+
+ #clock-cells = <0>;
+ clock-output-names = "usb3_uni_phy_pipe_clk_src";
+
+ #phy-cells = <0>;
+
+ status = "disabled";
+ };
+
system_noc: interconnect@1640000 {
compatible = "qcom,sdx75-system-noc";
reg = <0x0 0x01640000 0x0 0x4b400>;
@@ -497,6 +538,83 @@ tcsr_mutex: hwlock@1f40000 {
#hwlock-cells = <1>;
};
+ usb: usb@a6f8800 {
+ compatible = "qcom,sdx75-dwc3", "qcom,dwc3";
+ reg = <0x0 0x0a6f8800 0x0 0x400>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ clocks = <&gcc GCC_USB30_SLV_AHB_CLK>,
+ <&gcc GCC_USB30_MASTER_CLK>,
+ <&gcc GCC_USB30_MSTR_AXI_CLK>,
+ <&gcc GCC_USB30_SLEEP_CLK>,
+ <&gcc GCC_USB30_MOCK_UTMI_CLK>;
+ clock-names = "cfg_noc",
+ "core",
+ "iface",
+ "sleep",
+ "mock_utmi";
+
+ assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
+ <&gcc GCC_USB30_MASTER_CLK>;
+ assigned-clock-rates = <19200000>, <200000000>;
+
+ interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
+ <&pdc 17 IRQ_TYPE_LEVEL_HIGH>,
+ <&pdc 9 IRQ_TYPE_EDGE_RISING>,
+ <&pdc 10 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "hs_phy_irq",
+ "ss_phy_irq",
+ "dm_hs_phy_irq",
+ "dp_hs_phy_irq";
+
+ power-domains = <&gcc GCC_USB30_GDSC>;
+
+ resets = <&gcc GCC_USB30_BCR>;
+
+ interconnects = <&system_noc MASTER_USB3_0 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &system_noc SLAVE_USB3 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "usb-ddr",
+ "apps-usb";
+
+ status = "disabled";
+
+ usb_dwc3: usb@a600000 {
+ compatible = "snps,dwc3";
+ reg = <0x0 0x0a600000 0x0 0xcd00>;
+ interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
+ iommus = <&apps_smmu 0x80 0x0>;
+ snps,dis_u2_susphy_quirk;
+ snps,dis_enblslpm_quirk;
+ phys = <&usb_hsphy>,
+ <&usb_qmpphy>;
+ phy-names = "usb2-phy",
+ "usb3-phy";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ usb_1_dwc3_hs: endpoint {
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ usb_1_dwc3_ss: endpoint {
+ };
+ };
+ };
+ };
+ };
+
pdc: interrupt-controller@b220000 {
compatible = "qcom,sdx75-pdc", "qcom,pdc";
reg = <0x0 0xb220000 0x0 0x30000>,
--
2.25.1
On Fri, 17 Nov 2023 at 10:08, Rohit Agarwal <[email protected]> wrote:
>
> Add devicetree nodes for enabling USB3 controller, Qcom QMP PHY and
> HS PHY on SDX75.
>
> Signed-off-by: Rohit Agarwal <[email protected]>
> Acked-by: Konrad Dybcio <[email protected]>
> ---
> arch/arm64/boot/dts/qcom/sdx75.dtsi | 118 ++++++++++++++++++++++++++++
> 1 file changed, 118 insertions(+)
Reviewed-by: Dmitry Baryshkov <[email protected]>
--
With best wishes
Dmitry
On Fri, 17 Nov 2023 13:37:34 +0530, Rohit Agarwal wrote:
> Changes in v5:
> - Rebased on 6.7-rc1.
> - Collected the Ack tag.
>
> Changes in v4:
> - Reordered the interconnect to keep it in sorted order in patch 1/3.
>
> [...]
Applied, thanks!
[1/3] arm64: dts: qcom: Add interconnect nodes for SDX75
commit: ea72a527bd205283db08287cd49737e889788065
[2/3] arm64: dts: qcom: Add USB3 and PHY support on SDX75
commit: f47303a8d0b50e762930d4d09ea883fd741394ea
[3/3] arm64: dts: qcom: sdx75-idp: Enable USB3 and PHY support
commit: a8db1c061f8b4d6881253640119f651031eb3786
Best regards,
--
Bjorn Andersson <[email protected]>