Without setting the parent for SCLK_USB480M the clock will use xin24m as
it's default parent.
While this is generally not an issue for the usb blocks to work, it becomes
an issue for RK3128 since SCLK_USB480M can be a parent for other HW blocks
(GPU, VPU, VIO), but they will never chose it, since it is currently always
running at OSC frequency which is to slow for their needs.
This sets the usb2 phy's output as SCLK_USB480M's parent and it's users
can chose it if desired.
Signed-off-by: Alex Bee <[email protected]>
---
Changes in v3:
- moved parent assignment to the phy node
arch/arm/boot/dts/rockchip/rk3128.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/boot/dts/rockchip/rk3128.dtsi b/arch/arm/boot/dts/rockchip/rk3128.dtsi
index c8844e0024dc..61b292c7c4c3 100644
--- a/arch/arm/boot/dts/rockchip/rk3128.dtsi
+++ b/arch/arm/boot/dts/rockchip/rk3128.dtsi
@@ -266,6 +266,8 @@ usb2phy: usb2phy@17c {
clocks = <&cru SCLK_OTGPHY0>;
clock-names = "phyclk";
clock-output-names = "usb480m_phy";
+ assigned-clocks = <&cru SCLK_USB480M>;
+ assigned-clock-parents = <&usb2phy>;
#clock-cells = <0>;
status = "disabled";
--
2.42.0