Boot firmware on AMD's Yellow Carp and Pink Sardine allocates
very minimal buses for PCIe downstream ports. This results in
failure to extend the daisy chain.
Add quirk to reset the downstream port to help reset the topology
created by boot firmware.
Suggested-by: Mario Limonciello <[email protected]>
Signed-off-by: Sanath S <[email protected]>
Cc: <[email protected]>
---
drivers/thunderbolt/quirks.c | 14 ++++++++++++++
drivers/thunderbolt/switch.c | 28 ++++++++++++++++++++++++++++
drivers/thunderbolt/tb.h | 2 ++
drivers/thunderbolt/tb_regs.h | 1 +
4 files changed, 45 insertions(+)
diff --git a/drivers/thunderbolt/quirks.c b/drivers/thunderbolt/quirks.c
index e6bfa63b40ae..45e9d6c43e4a 100644
--- a/drivers/thunderbolt/quirks.c
+++ b/drivers/thunderbolt/quirks.c
@@ -27,6 +27,12 @@ static void quirk_clx_disable(struct tb_switch *sw)
tb_sw_dbg(sw, "disabling CL states\n");
}
+static void quirk_amd_downstream_port_reset(struct tb_switch *sw)
+{
+ sw->quirks |= QUIRK_DPR;
+ tb_sw_dbg(sw, "Resetting Down Stream Port\n");
+}
+
static void quirk_usb3_maximum_bandwidth(struct tb_switch *sw)
{
struct tb_port *port;
@@ -93,6 +99,14 @@ static const struct tb_quirk tb_quirks[] = {
{ 0x0438, 0x0209, 0x0000, 0x0000, quirk_clx_disable },
{ 0x0438, 0x020a, 0x0000, 0x0000, quirk_clx_disable },
{ 0x0438, 0x020b, 0x0000, 0x0000, quirk_clx_disable },
+ /*
+ * Reset Down Stream Ports on AMD USB4 Yellow Carp and
+ * Pink Sardine platforms.
+ */
+ { 0x0438, 0x0208, 0x0000, 0x0000, quirk_amd_downstream_port_reset },
+ { 0x0438, 0x0209, 0x0000, 0x0000, quirk_amd_downstream_port_reset },
+ { 0x0438, 0x020a, 0x0000, 0x0000, quirk_amd_downstream_port_reset },
+ { 0x0438, 0x020b, 0x0000, 0x0000, quirk_amd_downstream_port_reset },
};
/**
diff --git a/drivers/thunderbolt/switch.c b/drivers/thunderbolt/switch.c
index 1e15ffa79295..75780c6feea3 100644
--- a/drivers/thunderbolt/switch.c
+++ b/drivers/thunderbolt/switch.c
@@ -1547,6 +1547,23 @@ static void tb_dump_switch(const struct tb *tb, const struct tb_switch *sw)
regs->__unknown1, regs->__unknown4);
}
+static int tb_switch_reset_downstream_port(struct tb_switch *sw)
+{
+ struct tb_port *port;
+ uint32_t val = 0;
+ int ret;
+
+ tb_switch_for_each_port(sw, port) {
+ if (port->config.type == TB_TYPE_PORT) {
+ val = val | PORT_CS_19_DPR;
+ ret = tb_port_write(port, &val, TB_CFG_PORT,
+ port->cap_usb4 + PORT_CS_19, 1);
+ break;
+ }
+ }
+ return ret;
+}
+
/**
* tb_switch_reset() - reconfigure route, enable and send TB_CFG_PKG_RESET
* @sw: Switch to reset
@@ -3201,6 +3218,17 @@ int tb_switch_add(struct tb_switch *sw)
return ret;
}
+ /*
+ * PCIe resource allocated by boot firmware is not utilizing all the
+ * available buses, So perform reset of topology to avoid failure in
+ * extending daisy chain.
+ */
+ if (sw->quirks & QUIRK_DPR) {
+ ret = tb_switch_reset_downstream_port(sw);
+ if (ret)
+ return ret;
+ }
+
ret = tb_switch_port_hotplug_enable(sw);
if (ret)
return ret;
diff --git a/drivers/thunderbolt/tb.h b/drivers/thunderbolt/tb.h
index e299e53473ae..7a9ff53be67a 100644
--- a/drivers/thunderbolt/tb.h
+++ b/drivers/thunderbolt/tb.h
@@ -23,6 +23,8 @@
#define QUIRK_FORCE_POWER_LINK_CONTROLLER BIT(0)
/* Disable CLx if not supported */
#define QUIRK_NO_CLX BIT(1)
+/* Reset Down Stream Port */
+#define QUIRK_DPR BIT(2)
/**
* struct tb_nvm - Structure holding NVM information
diff --git a/drivers/thunderbolt/tb_regs.h b/drivers/thunderbolt/tb_regs.h
index 87e4795275fe..d49530bc0d53 100644
--- a/drivers/thunderbolt/tb_regs.h
+++ b/drivers/thunderbolt/tb_regs.h
@@ -389,6 +389,7 @@ struct tb_regs_port_header {
#define PORT_CS_18_CSA BIT(22)
#define PORT_CS_18_TIP BIT(24)
#define PORT_CS_19 0x13
+#define PORT_CS_19_DPR BIT(0)
#define PORT_CS_19_PC BIT(3)
#define PORT_CS_19_PID BIT(4)
#define PORT_CS_19_WOC BIT(16)
--
2.34.1
On Tue, Nov 21, 2023 at 11:17:01PM +0530, Sanath S wrote:
> Boot firmware on AMD's Yellow Carp and Pink Sardine allocates
> very minimal buses for PCIe downstream ports. This results in
> failure to extend the daisy chain.
>
> Add quirk to reset the downstream port to help reset the topology
> created by boot firmware.
>
> Suggested-by: Mario Limonciello <[email protected]>
> Signed-off-by: Sanath S <[email protected]>
> Cc: <[email protected]>
What commit id does this fix?
thanks,
greg k-h
On 11/21/2023 11:34 PM, Greg KH wrote:
> On Tue, Nov 21, 2023 at 11:17:01PM +0530, Sanath S wrote:
>> Boot firmware on AMD's Yellow Carp and Pink Sardine allocates
>> very minimal buses for PCIe downstream ports. This results in
>> failure to extend the daisy chain.
>>
>> Add quirk to reset the downstream port to help reset the topology
>> created by boot firmware.
>>
>> Suggested-by: Mario Limonciello <[email protected]>
>> Signed-off-by: Sanath S <[email protected]>
Fixes: e390909ac763("thunderbolt: Add vendor specific NHI quirk for
auto-clearing interrupt status")
>> Cc: <[email protected]>
> What commit id does this fix?
>
> thanks,
>
> greg k-h
>
Hi Sanath,
kernel test robot noticed the following build warnings:
[auto build test WARNING on westeri-thunderbolt/next]
[also build test WARNING on linus/master v6.7-rc2 next-20231121]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Sanath-S/thunderbolt-Add-quirk-to-reset-downstream-port/20231122-014913
base: https://git.kernel.org/pub/scm/linux/kernel/git/westeri/thunderbolt.git next
patch link: https://lore.kernel.org/r/20231121174701.3922587-1-Sanath.S%40amd.com
patch subject: [Patch] thunderbolt: Add quirk to reset downstream port
config: x86_64-buildonly-randconfig-003-20231122 (https://download.01.org/0day-ci/archive/20231122/[email protected]/config)
compiler: clang version 16.0.4 (https://github.com/llvm/llvm-project.git ae42196bc493ffe877a7e3dff8be32035dea4d07)
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20231122/[email protected]/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <[email protected]>
| Closes: https://lore.kernel.org/oe-kbuild-all/[email protected]/
All warnings (new ones prefixed by >>):
>> drivers/thunderbolt/switch.c:1556:2: warning: variable 'ret' is used uninitialized whenever 'for' loop exits because its condition is false [-Wsometimes-uninitialized]
tb_switch_for_each_port(sw, port) {
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
drivers/thunderbolt/tb.h:821:7: note: expanded from macro 'tb_switch_for_each_port'
(p) <= &(sw)->ports[(sw)->config.max_port_number]; (p)++)
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
drivers/thunderbolt/switch.c:1564:9: note: uninitialized use occurs here
return ret;
^~~
drivers/thunderbolt/switch.c:1556:2: note: remove the condition if it is always true
tb_switch_for_each_port(sw, port) {
^
drivers/thunderbolt/tb.h:821:7: note: expanded from macro 'tb_switch_for_each_port'
(p) <= &(sw)->ports[(sw)->config.max_port_number]; (p)++)
^
drivers/thunderbolt/switch.c:1554:9: note: initialize the variable 'ret' to silence this warning
int ret;
^
= 0
1 warning generated.
vim +1556 drivers/thunderbolt/switch.c
1549
1550 static int tb_switch_reset_downstream_port(struct tb_switch *sw)
1551 {
1552 struct tb_port *port;
1553 uint32_t val = 0;
1554 int ret;
1555
> 1556 tb_switch_for_each_port(sw, port) {
1557 if (port->config.type == TB_TYPE_PORT) {
1558 val = val | PORT_CS_19_DPR;
1559 ret = tb_port_write(port, &val, TB_CFG_PORT,
1560 port->cap_usb4 + PORT_CS_19, 1);
1561 break;
1562 }
1563 }
1564 return ret;
1565 }
1566
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki