This patchset adds some missing register offsets for the v6 and v6.20,
as well as the new v7 ones. These register offsets are used by the
new Qualcomm Snapdragon X Elite (X1E80100) platform.
Signed-off-by: Abel Vesa <[email protected]>
---
Abel Vesa (7):
phy: qcom-qmp: qserdes-com: Add some more v6 register offsets
phy: qcom-qmp: qserdes-txrx: Add some more v6.20 register offsets
phy: qcom-qmp: pcs: Add v7 register offsets
phy: qcom-qmp: pcs-usb: Add v7 register offsets
phy: qcom-qmp: qserdes-com: Add v7 register offsets
phy: qcom-qmp: qserdes-txrx: Add V6 N4 register offsets
phy: qcom-qmp: qserdes-txrx: Add v7 register offsets
drivers/phy/qualcomm/phy-qcom-qmp-pcs-usb-v7.h | 31 ++++++++
drivers/phy/qualcomm/phy-qcom-qmp-pcs-v7.h | 28 +++++++
drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h | 5 ++
drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v7.h | 86 ++++++++++++++++++++++
.../phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v6.h | 1 +
.../phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v6_20.h | 4 +
.../phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v6_n4.h | 51 +++++++++++++
.../phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v7.h | 78 ++++++++++++++++++++
drivers/phy/qualcomm/phy-qcom-qmp.h | 6 ++
9 files changed, 290 insertions(+)
---
base-commit: 07b677953b9dca02928be323e2db853511305fa9
change-id: 20231122-phy-qualcomm-v6-v6-20-v7-new-offsets-5ed528c88f62
Best regards,
--
Abel Vesa <[email protected]>
Add some missing V6 registers offsets that are needed by the new
Snapdragon X Elite (X1E80100) platform.
Signed-off-by: Abel Vesa <[email protected]>
---
drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h | 5 +++++
drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v6.h | 1 +
2 files changed, 6 insertions(+)
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h
index f420f8faf16a..ec7291424dd1 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h
@@ -22,6 +22,8 @@
#define QSERDES_V6_COM_DIV_FRAC_START2_MODE1 0x34
#define QSERDES_V6_COM_DIV_FRAC_START3_MODE1 0x38
#define QSERDES_V6_COM_HSCLK_SEL_1 0x3c
+#define QSERDES_V6_COM_INTEGLOOP_GAIN0_MODE1 0x40
+#define QSERDES_V6_COM_INTEGLOOP_GAIN1_MODE1 0x44
#define QSERDES_V6_COM_VCO_TUNE1_MODE1 0x48
#define QSERDES_V6_COM_VCO_TUNE2_MODE1 0x4c
#define QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE1 0x50
@@ -48,6 +50,7 @@
#define QSERDES_V6_COM_VCO_TUNE2_MODE0 0xac
#define QSERDES_V6_COM_BG_TIMER 0xbc
#define QSERDES_V6_COM_SSC_EN_CENTER 0xc0
+#define QSERDES_V6_COM_SSC_ADJ_PER1 0xc4
#define QSERDES_V6_COM_SSC_PER1 0xcc
#define QSERDES_V6_COM_SSC_PER2 0xd0
#define QSERDES_V6_COM_PLL_POST_DIV_MUX 0xd8
@@ -56,6 +59,7 @@
#define QSERDES_V6_COM_SYS_CLK_CTRL 0xe4
#define QSERDES_V6_COM_SYSCLK_BUF_ENABLE 0xe8
#define QSERDES_V6_COM_PLL_IVCO 0xf4
+#define QSERDES_V6_COM_PLL_IVCO_MODE1 0xf8
#define QSERDES_V6_COM_SYSCLK_EN_SEL 0x110
#define QSERDES_V6_COM_RESETSM_CNTRL 0x118
#define QSERDES_V6_COM_LOCK_CMP_EN 0x120
@@ -63,6 +67,7 @@
#define QSERDES_V6_COM_VCO_TUNE_CTRL 0x13c
#define QSERDES_V6_COM_VCO_TUNE_MAP 0x140
#define QSERDES_V6_COM_VCO_TUNE_INITVAL2 0x148
+#define QSERDES_V6_COM_VCO_TUNE_MAXVAL2 0x158
#define QSERDES_V6_COM_CLK_SELECT 0x164
#define QSERDES_V6_COM_CORE_CLK_EN 0x170
#define QSERDES_V6_COM_CMN_CONFIG_1 0x174
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v6.h
index 8883e1de730e..23ffcfae9efa 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v6.h
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v6.h
@@ -23,6 +23,7 @@
#define QSERDES_V6_TX_PARRATE_REC_DETECT_IDLE_EN 0x60
#define QSERDES_V6_TX_BIST_PATTERN7 0x7c
#define QSERDES_V6_TX_LANE_MODE_1 0x84
+#define QSERDES_V6_TX_LANE_MODE_2 0x88
#define QSERDES_V6_TX_LANE_MODE_3 0x8c
#define QSERDES_V6_TX_LANE_MODE_4 0x90
#define QSERDES_V6_TX_LANE_MODE_5 0x94
--
2.34.1
The X1E80100 platform bumps the HW version of QMP phy to v7 for USB and PCIE.
Add the new qserdes TX RX offsets in a dedicated header file.
Signed-off-by: Abel Vesa <[email protected]>
---
.../phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v7.h | 78 ++++++++++++++++++++++
drivers/phy/qualcomm/phy-qcom-qmp.h | 1 +
2 files changed, 79 insertions(+)
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v7.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v7.h
new file mode 100644
index 000000000000..14023f47a95c
--- /dev/null
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v7.h
@@ -0,0 +1,78 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2023, Linaro Limited
+ */
+
+#ifndef QCOM_PHY_QMP_QSERDES_TXRX_USB_V7_H_
+#define QCOM_PHY_QMP_QSERDES_TXRX_USB_V7_H_
+
+#define QSERDES_V7_TX_CLKBUF_ENABLE 0x08
+#define QSERDES_V7_TX_RESET_TSYNC_EN 0x1c
+#define QSERDES_V7_TX_PRE_STALL_LDO_BOOST_EN 0x20
+#define QSERDES_V7_TX_TX_BAND 0x24
+#define QSERDES_V7_TX_INTERFACE_SELECT 0x2c
+#define QSERDES_V7_TX_RES_CODE_LANE_TX 0x34
+#define QSERDES_V7_TX_RES_CODE_LANE_RX 0x38
+#define QSERDES_V7_TX_RES_CODE_LANE_OFFSET_TX 0x3c
+#define QSERDES_V7_TX_RES_CODE_LANE_OFFSET_RX 0x40
+#define QSERDES_V7_TX_PARRATE_REC_DETECT_IDLE_EN 0x60
+#define QSERDES_V7_TX_BIST_PATTERN7 0x7c
+#define QSERDES_V7_TX_LANE_MODE_1 0x84
+#define QSERDES_V7_TX_LANE_MODE_2 0x88
+#define QSERDES_V7_TX_LANE_MODE_3 0x8c
+#define QSERDES_V7_TX_LANE_MODE_4 0x90
+#define QSERDES_V7_TX_LANE_MODE_5 0x94
+#define QSERDES_V7_TX_RCV_DETECT_LVL_2 0xa4
+#define QSERDES_V7_TX_TRAN_DRVR_EMP_EN 0xc0
+#define QSERDES_V7_TX_TX_INTERFACE_MODE 0xc4
+#define QSERDES_V7_TX_VMODE_CTRL1 0xc8
+#define QSERDES_V7_TX_PI_QEC_CTRL 0xe4
+
+#define QSERDES_V7_RX_UCDR_FO_GAIN 0x08
+#define QSERDES_V7_RX_UCDR_SO_GAIN 0x14
+#define QSERDES_V7_RX_UCDR_FASTLOCK_FO_GAIN 0x30
+#define QSERDES_V7_RX_UCDR_SO_SATURATION_AND_ENABLE 0x34
+#define QSERDES_V7_RX_UCDR_FASTLOCK_COUNT_LOW 0x3c
+#define QSERDES_V7_RX_UCDR_FASTLOCK_COUNT_HIGH 0x40
+#define QSERDES_V7_RX_UCDR_PI_CONTROLS 0x44
+#define QSERDES_V7_RX_UCDR_SB2_THRESH1 0x4c
+#define QSERDES_V7_RX_UCDR_SB2_THRESH2 0x50
+#define QSERDES_V7_RX_UCDR_SB2_GAIN1 0x54
+#define QSERDES_V7_RX_UCDR_SB2_GAIN2 0x58
+#define QSERDES_V7_RX_AUX_DATA_TCOARSE_TFINE 0x60
+#define QSERDES_V7_RX_TX_ADAPT_POST_THRESH 0xcc
+#define QSERDES_V7_RX_VGA_CAL_CNTRL1 0xd4
+#define QSERDES_V7_RX_VGA_CAL_CNTRL2 0xd8
+#define QSERDES_V7_RX_GM_CAL 0xdc
+#define QSERDES_V7_RX_RX_EQU_ADAPTOR_CNTRL2 0xec
+#define QSERDES_V7_RX_RX_EQU_ADAPTOR_CNTRL3 0xf0
+#define QSERDES_V7_RX_RX_EQU_ADAPTOR_CNTRL4 0xf4
+#define QSERDES_V7_RX_RX_IDAC_TSETTLE_LOW 0xf8
+#define QSERDES_V7_RX_RX_IDAC_TSETTLE_HIGH 0xfc
+#define QSERDES_V7_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x110
+#define QSERDES_V7_RX_SIDGET_ENABLES 0x118
+#define QSERDES_V7_RX_SIGDET_CNTRL 0x11c
+#define QSERDES_V7_RX_SIGDET_DEGLITCH_CNTRL 0x124
+#define QSERDES_V7_RX_RX_MODE_00_LOW 0x15c
+#define QSERDES_V7_RX_RX_MODE_00_HIGH 0x160
+#define QSERDES_V7_RX_RX_MODE_00_HIGH2 0x164
+#define QSERDES_V7_RX_RX_MODE_00_HIGH3 0x168
+#define QSERDES_V7_RX_RX_MODE_00_HIGH4 0x16c
+#define QSERDES_V7_RX_RX_MODE_01_LOW 0x170
+#define QSERDES_V7_RX_RX_MODE_01_HIGH 0x174
+#define QSERDES_V7_RX_RX_MODE_01_HIGH2 0x178
+#define QSERDES_V7_RX_RX_MODE_01_HIGH3 0x17c
+#define QSERDES_V7_RX_RX_MODE_01_HIGH4 0x180
+#define QSERDES_V7_RX_RX_MODE_10_LOW 0x184
+#define QSERDES_V7_RX_RX_MODE_10_HIGH 0x188
+#define QSERDES_V7_RX_RX_MODE_10_HIGH2 0x18c
+#define QSERDES_V7_RX_RX_MODE_10_HIGH3 0x190
+#define QSERDES_V7_RX_RX_MODE_10_HIGH4 0x194
+#define QSERDES_V7_RX_DFE_EN_TIMER 0x1a0
+#define QSERDES_V7_RX_DFE_CTLE_POST_CAL_OFFSET 0x1a4
+#define QSERDES_V7_RX_DCC_CTRL1 0x1a8
+#define QSERDES_V7_RX_VTH_CODE 0x1b0
+#define QSERDES_V7_RX_SIGDET_CAL_CTRL1 0x1e4
+#define QSERDES_V7_RX_SIGDET_CAL_TRIM 0x1f8
+
+#endif
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.h b/drivers/phy/qualcomm/phy-qcom-qmp.h
index 63b3cbfcb50f..6923496cbfee 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp.h
+++ b/drivers/phy/qualcomm/phy-qcom-qmp.h
@@ -28,6 +28,7 @@
#include "phy-qcom-qmp-qserdes-ln-shrd-v6.h"
#include "phy-qcom-qmp-qserdes-com-v7.h"
+#include "phy-qcom-qmp-qserdes-txrx-v7.h"
#include "phy-qcom-qmp-qserdes-pll.h"
--
2.34.1
On Wed, 22 Nov 2023 at 12:04, Abel Vesa <[email protected]> wrote:
>
> Add some missing V6 registers offsets that are needed by the new
> Snapdragon X Elite (X1E80100) platform.
>
> Signed-off-by: Abel Vesa <[email protected]>
> ---
> drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h | 5 +++++
> drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v6.h | 1 +
> 2 files changed, 6 insertions(+)
Reviewed-by: Dmitry Baryshkov <[email protected]>
--
With best wishes
Dmitry
On Wed, 22 Nov 2023 at 12:04, Abel Vesa <[email protected]> wrote:
>
> The X1E80100 platform bumps the HW version of QMP phy to v7 for USB and PCIE.
> Add the new qserdes TX RX offsets in a dedicated header file.
>
> Signed-off-by: Abel Vesa <[email protected]>
> ---
> .../phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v7.h | 78 ++++++++++++++++++++++
> drivers/phy/qualcomm/phy-qcom-qmp.h | 1 +
> 2 files changed, 79 insertions(+)
>
> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v7.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v7.h
> new file mode 100644
> index 000000000000..14023f47a95c
> --- /dev/null
> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v7.h
> @@ -0,0 +1,78 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * Copyright (c) 2023, Linaro Limited
> + */
> +
> +#ifndef QCOM_PHY_QMP_QSERDES_TXRX_USB_V7_H_
> +#define QCOM_PHY_QMP_QSERDES_TXRX_USB_V7_H_
s/_USB//
> +
> +#define QSERDES_V7_TX_CLKBUF_ENABLE 0x08
> +#define QSERDES_V7_TX_RESET_TSYNC_EN 0x1c
> +#define QSERDES_V7_TX_PRE_STALL_LDO_BOOST_EN 0x20
> +#define QSERDES_V7_TX_TX_BAND 0x24
> +#define QSERDES_V7_TX_INTERFACE_SELECT 0x2c
> +#define QSERDES_V7_TX_RES_CODE_LANE_TX 0x34
> +#define QSERDES_V7_TX_RES_CODE_LANE_RX 0x38
> +#define QSERDES_V7_TX_RES_CODE_LANE_OFFSET_TX 0x3c
> +#define QSERDES_V7_TX_RES_CODE_LANE_OFFSET_RX 0x40
> +#define QSERDES_V7_TX_PARRATE_REC_DETECT_IDLE_EN 0x60
> +#define QSERDES_V7_TX_BIST_PATTERN7 0x7c
> +#define QSERDES_V7_TX_LANE_MODE_1 0x84
> +#define QSERDES_V7_TX_LANE_MODE_2 0x88
> +#define QSERDES_V7_TX_LANE_MODE_3 0x8c
> +#define QSERDES_V7_TX_LANE_MODE_4 0x90
> +#define QSERDES_V7_TX_LANE_MODE_5 0x94
> +#define QSERDES_V7_TX_RCV_DETECT_LVL_2 0xa4
> +#define QSERDES_V7_TX_TRAN_DRVR_EMP_EN 0xc0
> +#define QSERDES_V7_TX_TX_INTERFACE_MODE 0xc4
> +#define QSERDES_V7_TX_VMODE_CTRL1 0xc8
> +#define QSERDES_V7_TX_PI_QEC_CTRL 0xe4
> +
> +#define QSERDES_V7_RX_UCDR_FO_GAIN 0x08
> +#define QSERDES_V7_RX_UCDR_SO_GAIN 0x14
> +#define QSERDES_V7_RX_UCDR_FASTLOCK_FO_GAIN 0x30
> +#define QSERDES_V7_RX_UCDR_SO_SATURATION_AND_ENABLE 0x34
> +#define QSERDES_V7_RX_UCDR_FASTLOCK_COUNT_LOW 0x3c
> +#define QSERDES_V7_RX_UCDR_FASTLOCK_COUNT_HIGH 0x40
> +#define QSERDES_V7_RX_UCDR_PI_CONTROLS 0x44
> +#define QSERDES_V7_RX_UCDR_SB2_THRESH1 0x4c
> +#define QSERDES_V7_RX_UCDR_SB2_THRESH2 0x50
> +#define QSERDES_V7_RX_UCDR_SB2_GAIN1 0x54
> +#define QSERDES_V7_RX_UCDR_SB2_GAIN2 0x58
> +#define QSERDES_V7_RX_AUX_DATA_TCOARSE_TFINE 0x60
> +#define QSERDES_V7_RX_TX_ADAPT_POST_THRESH 0xcc
> +#define QSERDES_V7_RX_VGA_CAL_CNTRL1 0xd4
> +#define QSERDES_V7_RX_VGA_CAL_CNTRL2 0xd8
> +#define QSERDES_V7_RX_GM_CAL 0xdc
> +#define QSERDES_V7_RX_RX_EQU_ADAPTOR_CNTRL2 0xec
> +#define QSERDES_V7_RX_RX_EQU_ADAPTOR_CNTRL3 0xf0
> +#define QSERDES_V7_RX_RX_EQU_ADAPTOR_CNTRL4 0xf4
> +#define QSERDES_V7_RX_RX_IDAC_TSETTLE_LOW 0xf8
> +#define QSERDES_V7_RX_RX_IDAC_TSETTLE_HIGH 0xfc
> +#define QSERDES_V7_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x110
> +#define QSERDES_V7_RX_SIDGET_ENABLES 0x118
> +#define QSERDES_V7_RX_SIGDET_CNTRL 0x11c
> +#define QSERDES_V7_RX_SIGDET_DEGLITCH_CNTRL 0x124
> +#define QSERDES_V7_RX_RX_MODE_00_LOW 0x15c
> +#define QSERDES_V7_RX_RX_MODE_00_HIGH 0x160
> +#define QSERDES_V7_RX_RX_MODE_00_HIGH2 0x164
> +#define QSERDES_V7_RX_RX_MODE_00_HIGH3 0x168
> +#define QSERDES_V7_RX_RX_MODE_00_HIGH4 0x16c
> +#define QSERDES_V7_RX_RX_MODE_01_LOW 0x170
> +#define QSERDES_V7_RX_RX_MODE_01_HIGH 0x174
> +#define QSERDES_V7_RX_RX_MODE_01_HIGH2 0x178
> +#define QSERDES_V7_RX_RX_MODE_01_HIGH3 0x17c
> +#define QSERDES_V7_RX_RX_MODE_01_HIGH4 0x180
> +#define QSERDES_V7_RX_RX_MODE_10_LOW 0x184
> +#define QSERDES_V7_RX_RX_MODE_10_HIGH 0x188
> +#define QSERDES_V7_RX_RX_MODE_10_HIGH2 0x18c
> +#define QSERDES_V7_RX_RX_MODE_10_HIGH3 0x190
> +#define QSERDES_V7_RX_RX_MODE_10_HIGH4 0x194
> +#define QSERDES_V7_RX_DFE_EN_TIMER 0x1a0
> +#define QSERDES_V7_RX_DFE_CTLE_POST_CAL_OFFSET 0x1a4
> +#define QSERDES_V7_RX_DCC_CTRL1 0x1a8
> +#define QSERDES_V7_RX_VTH_CODE 0x1b0
> +#define QSERDES_V7_RX_SIGDET_CAL_CTRL1 0x1e4
> +#define QSERDES_V7_RX_SIGDET_CAL_TRIM 0x1f8
> +
> +#endif
> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.h b/drivers/phy/qualcomm/phy-qcom-qmp.h
> index 63b3cbfcb50f..6923496cbfee 100644
> --- a/drivers/phy/qualcomm/phy-qcom-qmp.h
> +++ b/drivers/phy/qualcomm/phy-qcom-qmp.h
> @@ -28,6 +28,7 @@
> #include "phy-qcom-qmp-qserdes-ln-shrd-v6.h"
>
> #include "phy-qcom-qmp-qserdes-com-v7.h"
> +#include "phy-qcom-qmp-qserdes-txrx-v7.h"
>
> #include "phy-qcom-qmp-qserdes-pll.h"
>
>
> --
> 2.34.1
>
>
--
With best wishes
Dmitry