This series adds support for the StarFive JH7100 SoC to the SiFive cache
controller driver. The JH7100 was a "development version" of the JH7110
used on the BeagleV Starlight and VisionFive V1 boards. It has
non-coherent peripheral DMAs but was designed before the standard RISC-V
Zicbom extension, so it neeeds support in this driver for non-standard
cache management.
Since v1:
- Fix email threading, hopefully.
- Drop sifive,ccache-ops device tree property and just match on the
compatible. (Conor)
Emil Renner Berthing (2):
dt-bindings: cache: sifive,ccache0: Add StarFive JH7100 compatible
soc: sifive: ccache: Add StarFive JH7100 support
.../bindings/cache/sifive,ccache0.yaml | 6 +-
drivers/soc/sifive/sifive_ccache.c | 62 ++++++++++++++++++-
2 files changed, 65 insertions(+), 3 deletions(-)
--
2.40.1
From: Emil Renner Berthing <[email protected]>
This adds support for the StarFive JH7100 SoC which also features this
SiFive cache controller.
The JH7100 has non-coherent DMAs but predate the standard RISC-V Zicbom
exension, so instead we need to use this cache controller for
non-standard cache management operations.
Unfortunately the interrupt for uncorrected data is broken on the JH7100
and fires continuously, so add a quirk to not register a handler for it.
Signed-off-by: Emil Renner Berthing <[email protected]>
---
drivers/soc/sifive/sifive_ccache.c | 62 +++++++++++++++++++++++++++++-
1 file changed, 60 insertions(+), 2 deletions(-)
diff --git a/drivers/soc/sifive/sifive_ccache.c b/drivers/soc/sifive/sifive_ccache.c
index 3684f5b40a80..0da3d1bd0866 100644
--- a/drivers/soc/sifive/sifive_ccache.c
+++ b/drivers/soc/sifive/sifive_ccache.c
@@ -8,13 +8,16 @@
#define pr_fmt(fmt) "CCACHE: " fmt
+#include <linux/align.h>
#include <linux/debugfs.h>
#include <linux/interrupt.h>
#include <linux/of_irq.h>
#include <linux/of_address.h>
#include <linux/device.h>
#include <linux/bitfield.h>
+#include <asm/cacheflush.h>
#include <asm/cacheinfo.h>
+#include <asm/dma-noncoherent.h>
#include <soc/sifive/sifive_ccache.h>
#define SIFIVE_CCACHE_DIRECCFIX_LOW 0x100
@@ -39,10 +42,14 @@
#define SIFIVE_CCACHE_CONFIG_SETS_MASK GENMASK_ULL(23, 16)
#define SIFIVE_CCACHE_CONFIG_BLKS_MASK GENMASK_ULL(31, 24)
+#define SIFIVE_CCACHE_FLUSH64 0x200
+#define SIFIVE_CCACHE_FLUSH32 0x240
+
#define SIFIVE_CCACHE_WAYENABLE 0x08
#define SIFIVE_CCACHE_ECCINJECTERR 0x40
#define SIFIVE_CCACHE_MAX_ECCINTR 4
+#define SIFIVE_CCACHE_LINE_SIZE 64
static void __iomem *ccache_base;
static int g_irq[SIFIVE_CCACHE_MAX_ECCINTR];
@@ -56,6 +63,11 @@ enum {
DIR_UNCORR,
};
+enum {
+ QUIRK_NONSTANDARD_CACHE_OPS = BIT(0),
+ QUIRK_BROKEN_DATA_UNCORR = BIT(1),
+};
+
#ifdef CONFIG_DEBUG_FS
static struct dentry *sifive_test;
@@ -106,6 +118,8 @@ static void ccache_config_read(void)
static const struct of_device_id sifive_ccache_ids[] = {
{ .compatible = "sifive,fu540-c000-ccache" },
{ .compatible = "sifive,fu740-c000-ccache" },
+ { .compatible = "starfive,jh7100-ccache",
+ .data = (void *)(QUIRK_NONSTANDARD_CACHE_OPS | QUIRK_BROKEN_DATA_UNCORR) },
{ .compatible = "sifive,ccache0" },
{ /* end of table */ }
};
@@ -124,6 +138,34 @@ int unregister_sifive_ccache_error_notifier(struct notifier_block *nb)
}
EXPORT_SYMBOL_GPL(unregister_sifive_ccache_error_notifier);
+#ifdef CONFIG_RISCV_NONSTANDARD_CACHE_OPS
+static void ccache_flush_range(phys_addr_t start, size_t len)
+{
+ phys_addr_t end = start + len;
+ phys_addr_t line;
+
+ if (!len)
+ return;
+
+ mb();
+ for (line = ALIGN_DOWN(start, SIFIVE_CCACHE_LINE_SIZE); line < end;
+ line += SIFIVE_CCACHE_LINE_SIZE) {
+#ifdef CONFIG_32BIT
+ writel(line >> 4, ccache_base + SIFIVE_CCACHE_FLUSH32);
+#else
+ writeq(line, ccache_base + SIFIVE_CCACHE_FLUSH64);
+#endif
+ mb();
+ }
+}
+
+static const struct riscv_nonstd_cache_ops ccache_mgmt_ops __initdata = {
+ .wback = &ccache_flush_range,
+ .inv = &ccache_flush_range,
+ .wback_inv = &ccache_flush_range,
+};
+#endif /* CONFIG_RISCV_NONSTANDARD_CACHE_OPS */
+
static int ccache_largest_wayenabled(void)
{
return readl(ccache_base + SIFIVE_CCACHE_WAYENABLE) & 0xFF;
@@ -210,11 +252,15 @@ static int __init sifive_ccache_init(void)
struct device_node *np;
struct resource res;
int i, rc, intr_num;
+ const struct of_device_id *match;
+ unsigned long quirks;
- np = of_find_matching_node(NULL, sifive_ccache_ids);
+ np = of_find_matching_node_and_match(NULL, sifive_ccache_ids, &match);
if (!np)
return -ENODEV;
+ quirks = (uintptr_t)match->data;
+
if (of_address_to_resource(np, 0, &res)) {
rc = -ENODEV;
goto err_node_put;
@@ -240,6 +286,10 @@ static int __init sifive_ccache_init(void)
for (i = 0; i < intr_num; i++) {
g_irq[i] = irq_of_parse_and_map(np, i);
+
+ if (i == DATA_UNCORR && (quirks & QUIRK_BROKEN_DATA_UNCORR))
+ continue;
+
rc = request_irq(g_irq[i], ccache_int_handler, 0, "ccache_ecc",
NULL);
if (rc) {
@@ -249,6 +299,14 @@ static int __init sifive_ccache_init(void)
}
of_node_put(np);
+#ifdef CONFIG_RISCV_NONSTANDARD_CACHE_OPS
+ if (quirks & QUIRK_NONSTANDARD_CACHE_OPS) {
+ riscv_cbom_block_size = SIFIVE_CCACHE_LINE_SIZE;
+ riscv_noncoherent_supported();
+ riscv_noncoherent_register_cache_ops(&ccache_mgmt_ops);
+ }
+#endif
+
ccache_config_read();
ccache_cache_ops.get_priv_group = ccache_get_priv_group;
@@ -269,4 +327,4 @@ static int __init sifive_ccache_init(void)
return rc;
}
-device_initcall(sifive_ccache_init);
+arch_initcall(sifive_ccache_init);
--
2.40.1
This cache controller is also used on the StarFive JH7100 SoC.
Unfortunately it needs a quirk to work properly, so add dedicated
compatible string to be able to match it.
Signed-off-by: Emil Renner Berthing <[email protected]>
---
Documentation/devicetree/bindings/cache/sifive,ccache0.yaml | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/cache/sifive,ccache0.yaml b/Documentation/devicetree/bindings/cache/sifive,ccache0.yaml
index 8a6a78e1a7ab..7e8cebe21584 100644
--- a/Documentation/devicetree/bindings/cache/sifive,ccache0.yaml
+++ b/Documentation/devicetree/bindings/cache/sifive,ccache0.yaml
@@ -38,7 +38,9 @@ properties:
- sifive,fu740-c000-ccache
- const: cache
- items:
- - const: starfive,jh7110-ccache
+ - enum:
+ - starfive,jh7100-ccache
+ - starfive,jh7110-ccache
- const: sifive,ccache0
- const: cache
- items:
@@ -88,6 +90,7 @@ allOf:
contains:
enum:
- sifive,fu740-c000-ccache
+ - starfive,jh7100-ccache
- starfive,jh7110-ccache
- microchip,mpfs-ccache
@@ -111,6 +114,7 @@ allOf:
contains:
enum:
- sifive,fu740-c000-ccache
+ - starfive,jh7100-ccache
- starfive,jh7110-ccache
then:
--
2.40.1
On Tue, Oct 31, 2023 at 03:14:42PM +0100, Emil Renner Berthing wrote:
> This series adds support for the StarFive JH7100 SoC to the SiFive cache
> controller driver. The JH7100 was a "development version" of the JH7110
> used on the BeagleV Starlight and VisionFive V1 boards. It has
> non-coherent peripheral DMAs but was designed before the standard RISC-V
> Zicbom extension, so it neeeds support in this driver for non-standard
> cache management.
>
> Since v1:
> - Fix email threading, hopefully.
> - Drop sifive,ccache-ops device tree property and just match on the
> compatible. (Conor)
I'll grab these after the mw, presuming nothing comes up in the interim.
On Tue, Oct 31, 2023 at 03:14:44PM +0100, Emil Renner Berthing wrote:
> From: Emil Renner Berthing <[email protected]>
>
> This adds support for the StarFive JH7100 SoC which also features this
> SiFive cache controller.
>
> The JH7100 has non-coherent DMAs but predate the standard RISC-V Zicbom
> exension, so instead we need to use this cache controller for
> non-standard cache management operations.
>
> Unfortunately the interrupt for uncorrected data is broken on the JH7100
> and fires continuously, so add a quirk to not register a handler for it.
>
> Signed-off-by: Emil Renner Berthing <[email protected]>
> ---
> drivers/soc/sifive/sifive_ccache.c | 62 +++++++++++++++++++++++++++++-
> 1 file changed, 60 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/soc/sifive/sifive_ccache.c b/drivers/soc/sifive/sifive_ccache.c
> index 3684f5b40a80..0da3d1bd0866 100644
> --- a/drivers/soc/sifive/sifive_ccache.c
> +++ b/drivers/soc/sifive/sifive_ccache.c
> @@ -8,13 +8,16 @@
>
> #define pr_fmt(fmt) "CCACHE: " fmt
>
> +#include <linux/align.h>
> #include <linux/debugfs.h>
> #include <linux/interrupt.h>
> #include <linux/of_irq.h>
> #include <linux/of_address.h>
> #include <linux/device.h>
> #include <linux/bitfield.h>
> +#include <asm/cacheflush.h>
> #include <asm/cacheinfo.h>
> +#include <asm/dma-noncoherent.h>
> #include <soc/sifive/sifive_ccache.h>
>
> #define SIFIVE_CCACHE_DIRECCFIX_LOW 0x100
> @@ -39,10 +42,14 @@
> #define SIFIVE_CCACHE_CONFIG_SETS_MASK GENMASK_ULL(23, 16)
> #define SIFIVE_CCACHE_CONFIG_BLKS_MASK GENMASK_ULL(31, 24)
>
> +#define SIFIVE_CCACHE_FLUSH64 0x200
> +#define SIFIVE_CCACHE_FLUSH32 0x240
> +
> #define SIFIVE_CCACHE_WAYENABLE 0x08
> #define SIFIVE_CCACHE_ECCINJECTERR 0x40
>
> #define SIFIVE_CCACHE_MAX_ECCINTR 4
> +#define SIFIVE_CCACHE_LINE_SIZE 64
>
> static void __iomem *ccache_base;
> static int g_irq[SIFIVE_CCACHE_MAX_ECCINTR];
> @@ -56,6 +63,11 @@ enum {
> DIR_UNCORR,
> };
>
> +enum {
> + QUIRK_NONSTANDARD_CACHE_OPS = BIT(0),
> + QUIRK_BROKEN_DATA_UNCORR = BIT(1),
> +};
> +
> #ifdef CONFIG_DEBUG_FS
> static struct dentry *sifive_test;
>
> @@ -106,6 +118,8 @@ static void ccache_config_read(void)
> static const struct of_device_id sifive_ccache_ids[] = {
> { .compatible = "sifive,fu540-c000-ccache" },
> { .compatible = "sifive,fu740-c000-ccache" },
> + { .compatible = "starfive,jh7100-ccache",
> + .data = (void *)(QUIRK_NONSTANDARD_CACHE_OPS | QUIRK_BROKEN_DATA_UNCORR) },
> { .compatible = "sifive,ccache0" },
> { /* end of table */ }
> };
> @@ -124,6 +138,34 @@ int unregister_sifive_ccache_error_notifier(struct notifier_block *nb)
> }
> EXPORT_SYMBOL_GPL(unregister_sifive_ccache_error_notifier);
>
> +#ifdef CONFIG_RISCV_NONSTANDARD_CACHE_OPS
> +static void ccache_flush_range(phys_addr_t start, size_t len)
> +{
> + phys_addr_t end = start + len;
> + phys_addr_t line;
> +
> + if (!len)
> + return;
> +
> + mb();
Apparently memory barriers are supposed to be commented as to why they
are required.
I'm not sure if I care about that particular checkpatch complaint here.
> + for (line = ALIGN_DOWN(start, SIFIVE_CCACHE_LINE_SIZE); line < end;
> + line += SIFIVE_CCACHE_LINE_SIZE) {
> +#ifdef CONFIG_32BIT
> + writel(line >> 4, ccache_base + SIFIVE_CCACHE_FLUSH32);
> +#else
> + writeq(line, ccache_base + SIFIVE_CCACHE_FLUSH64);
> +#endif
> + mb();
> + }
> +}
> +
> +static const struct riscv_nonstd_cache_ops ccache_mgmt_ops __initdata = {
And apparently this should be __initconst rather than __initdata. I can
squash that in.
Cheers,
Conor.
From: Conor Dooley <[email protected]>
On Tue, 31 Oct 2023 15:14:42 +0100, Emil Renner Berthing wrote:
> This series adds support for the StarFive JH7100 SoC to the SiFive cache
> controller driver. The JH7100 was a "development version" of the JH7110
> used on the BeagleV Starlight and VisionFive V1 boards. It has
> non-coherent peripheral DMAs but was designed before the standard RISC-V
> Zicbom extension, so it neeeds support in this driver for non-standard
> cache management.
>
> [...]
Applied to riscv-cache-for-next, thanks! I still need to figure out how
I want to put things into linux-next as Arnd wants these cache driver
things in a PR of their own.
[1/2] dt-bindings: cache: sifive,ccache0: Add StarFive JH7100 compatible
https://git.kernel.org/conor/c/3d70b9853b44
[2/2] soc: sifive: ccache: Add StarFive JH7100 support
https://git.kernel.org/conor/c/0d5701dc9cd6
Thanks,
Conor.