The V3s (and related platforms) come with an instance of the A31 ISP.
Even though it is very close to the A31 ISP, it is not exactly
register-compatible and a dedicated compatible only is used as a
result.
Just like most other blocks of the camera pipeline, the ISP uses
the common CSI bus, module and ram clock as well as reset.
A port connection to the ISP is added to CSI0 for convenience since
CSI0 serves for MIPI CSI-2 interface support, which is likely to
receive raw data that will need to be processed by the ISP to produce
a final image.
The interconnects property is used to inherit the proper DMA offset.
Signed-off-by: Paul Kocialkowski <[email protected]>
---
arch/arm/boot/dts/allwinner/sun8i-v3s.dtsi | 35 ++++++++++++++++++++++
1 file changed, 35 insertions(+)
diff --git a/arch/arm/boot/dts/allwinner/sun8i-v3s.dtsi b/arch/arm/boot/dts/allwinner/sun8i-v3s.dtsi
index d57612023aa4..1a1dcd36cba4 100644
--- a/arch/arm/boot/dts/allwinner/sun8i-v3s.dtsi
+++ b/arch/arm/boot/dts/allwinner/sun8i-v3s.dtsi
@@ -645,6 +645,14 @@ csi0_in_mipi_csi2: endpoint {
remote-endpoint = <&mipi_csi2_out_csi0>;
};
};
+
+ port@2 {
+ reg = <2>;
+
+ csi0_out_isp: endpoint {
+ remote-endpoint = <&isp_in_csi0>;
+ };
+ };
};
};
@@ -703,5 +711,32 @@ csi1: camera@1cb4000 {
resets = <&ccu RST_BUS_CSI>;
status = "disabled";
};
+
+ isp: isp@1cb8000 {
+ compatible = "allwinner,sun8i-v3s-isp";
+ reg = <0x01cb8000 0x1000>;
+ interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_CSI>,
+ <&ccu CLK_CSI1_SCLK>,
+ <&ccu CLK_DRAM_CSI>;
+ clock-names = "bus", "mod", "ram";
+ resets = <&ccu RST_BUS_CSI>;
+ interconnects = <&mbus 5>;
+ interconnect-names = "dma-mem";
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ isp_in_csi0: endpoint {
+ remote-endpoint = <&csi0_out_isp>;
+ };
+ };
+ };
+ };
};
};
--
2.42.1
On Wednesday, November 22, 2023 3:14:22 PM CET Paul Kocialkowski wrote:
> The V3s (and related platforms) come with an instance of the A31 ISP.
> Even though it is very close to the A31 ISP, it is not exactly
> register-compatible and a dedicated compatible only is used as a
> result.
>
> Just like most other blocks of the camera pipeline, the ISP uses
> the common CSI bus, module and ram clock as well as reset.
>
> A port connection to the ISP is added to CSI0 for convenience since
> CSI0 serves for MIPI CSI-2 interface support, which is likely to
> receive raw data that will need to be processed by the ISP to produce
> a final image.
>
> The interconnects property is used to inherit the proper DMA offset.
>
> Signed-off-by: Paul Kocialkowski <[email protected]>
> ---
> arch/arm/boot/dts/allwinner/sun8i-v3s.dtsi | 35 ++++++++++++++++++++++
> 1 file changed, 35 insertions(+)
>
> diff --git a/arch/arm/boot/dts/allwinner/sun8i-v3s.dtsi b/arch/arm/boot/dts/allwinner/sun8i-v3s.dtsi
> index d57612023aa4..1a1dcd36cba4 100644
> --- a/arch/arm/boot/dts/allwinner/sun8i-v3s.dtsi
> +++ b/arch/arm/boot/dts/allwinner/sun8i-v3s.dtsi
> @@ -645,6 +645,14 @@ csi0_in_mipi_csi2: endpoint {
> remote-endpoint = <&mipi_csi2_out_csi0>;
> };
> };
> +
> + port@2 {
> + reg = <2>;
> +
> + csi0_out_isp: endpoint {
> + remote-endpoint = <&isp_in_csi0>;
> + };
> + };
> };
> };
>
> @@ -703,5 +711,32 @@ csi1: camera@1cb4000 {
> resets = <&ccu RST_BUS_CSI>;
> status = "disabled";
> };
> +
> + isp: isp@1cb8000 {
> + compatible = "allwinner,sun8i-v3s-isp";
> + reg = <0x01cb8000 0x1000>;
> + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ccu CLK_BUS_CSI>,
> + <&ccu CLK_CSI1_SCLK>,
> + <&ccu CLK_DRAM_CSI>;
> + clock-names = "bus", "mod", "ram";
> + resets = <&ccu RST_BUS_CSI>;
> + interconnects = <&mbus 5>;
> + interconnect-names = "dma-mem";
Same as in previous patch, interconnects properties are not described in
bindings, please update.
Best regards,
Jernej
> + status = "disabled";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> +
> + isp_in_csi0: endpoint {
> + remote-endpoint = <&csi0_out_isp>;
> + };
> + };
> + };
> + };
> };
> };
>