2023-11-24 13:29:14

by Alvin Šipraga

Subject: [PATCH v6 2/3] dt-bindings: clock: si5351: add PLL reset mode property

From: Alvin Šipraga <[email protected]>

For applications where the PLL must be adjusted without glitches in the
clock output(s), a new silabs,pll-reset-mode property is added. It
can be used to specify whether or not the PLL should be reset after
adjustment. Resetting is known to cause glitches.

For compatibility with older device trees, it must be assumed that the
default PLL reset mode is to unconditionally reset after adjustment.

Cc: Sebastian Hesselbarth <[email protected]>
Cc: Rabeeh Khoury <[email protected]>
Cc: Jacob Siverskog <[email protected]>
Cc: Sergej Sawazki <[email protected]>
Reviewed-by: Rob Herring <[email protected]>
Signed-off-by: Alvin Šipraga <[email protected]>
---
.../devicetree/bindings/clock/silabs,si5351.yaml | 24 ++++++++++++++++++++++
1 file changed, 24 insertions(+)

diff --git a/Documentation/devicetree/bindings/clock/silabs,si5351.yaml b/Documentation/devicetree/bindings/clock/silabs,si5351.yaml
index 494fa49a0c1b..d3e0ec29993b 100644
--- a/Documentation/devicetree/bindings/clock/silabs,si5351.yaml
+++ b/Documentation/devicetree/bindings/clock/silabs,si5351.yaml
@@ -62,6 +62,27 @@ properties:
- description: PLL source, XTAL (0) or CLKIN (1, Si5351C only).
enum: [ 0, 1 ]

+ silabs,pll-reset-mode:
+ $ref: /schemas/types.yaml#/definitions/uint32-matrix
+ minItems: 1
+ maxItems: 2
+ description: A list of cell pairs containing a PLL index and its reset mode.
+ items:
+ items:
+ - description: PLL A (0) or PLL B (1)
+ enum: [ 0, 1 ]
+ - description: |
+ Reset mode for the PLL. Mode can be one of:
+
+ 0 - reset whenever PLL rate is adjusted (default mode)
+ 1 - do not reset when PLL rate is adjusted
+
+ In mode 1, the PLL is only reset if the silabs,pll-reset is
+ specified in one of the clock output child nodes that also sources
+ the PLL. This mode may be preferable if output clocks are expected
+ to be adjusted without glitches.
+ enum: [ 0, 1 ]
+
patternProperties:
"^clkout@[0-7]$":
type: object
@@ -195,6 +216,9 @@ examples:
/* Use XTAL input as source of PLL0 and PLL1 */
silabs,pll-source = <0 0>, <1 0>;

+ /* Don't reset PLL1 on rate adjustment */
+ silabs,pll-reset-mode = <1 1>;
+
/*
* Overwrite CLK0 configuration with:
* - 8 mA output drive strength

--
2.42.1

2023-12-18 06:32:39

by Stephen Boyd

Subject: Re: [PATCH v6 2/3] dt-bindings: clock: si5351: add PLL reset mode property

Quoting Alvin Šipraga (2023-11-24 05:17:43)
> From: Alvin Šipraga <[email protected]>
>
> For applications where the PLL must be adjusted without glitches in the
> clock output(s), a new silabs,pll-reset-mode property is added. It
> can be used to specify whether or not the PLL should be reset after
> adjustment. Resetting is known to cause glitches.
>
> For compatibility with older device trees, it must be assumed that the
> default PLL reset mode is to unconditionally reset after adjustment.
>
> Cc: Sebastian Hesselbarth <[email protected]>
> Cc: Rabeeh Khoury <[email protected]>
> Cc: Jacob Siverskog <[email protected]>
> Cc: Sergej Sawazki <[email protected]>
> Reviewed-by: Rob Herring <[email protected]>
> Signed-off-by: Alvin Šipraga <[email protected]>
> ---

Applied to clk-next