Hi,
This patch series is pretty similar to the v1 version. I've named
it v3 because I've already sent a v2 patch as a reply to the message with
[PATCH 1/5]. The problem is, that this v2 patch is broken and
should be ignored. Sorry for that.
Jan
Changes since v1:
[PATCH 1/5]:
Complete a terminated descriptor with dma_cookie_complete()
Don't reinitialize temporary list head in xdma_terminate_all()
[PATCH 4/5]:
Fix incorrect text wrapping
Changes since v2:
[PATCH 1/5]:
DO NOT schedule callback from within xdma_terminate_all()
Here's the original message:
Hi,
This patch series introduces a couple of xdma driver enhancements, such
as two dmaengine callbacks, partial rework of a interrupt service
routine and loosening of dma_pool alignment requirements. I have tested
these changes with XDMA v4.1 (Rev. 20) block.
Jan
---
Jan Kuliga (5):
dmaengine: xilinx: xdma: Add transfer termination callbacks
dmaengine: xilinx: xdma: Get rid of duplicated macros definitions
dmaengine: xilinx: xdma: Complete lacking register description
dmaengine: xilinx: xdma: Rework xdma_channel_isr()
dmaengine: xilinx: xdma: Ease dma_pool alignment requirements
drivers/dma/xilinx/xdma-regs.h | 24 ++++------
drivers/dma/xilinx/xdma.c | 82 +++++++++++++++++++++++++++++-----
2 files changed, 80 insertions(+), 26 deletions(-)
base-commit: 98b1cc82c4affc16f5598d4fa14b1858671b2263
--
2.34.1
Complete lacking bits, that describe the status/control register values.
Signed-off-by: Jan Kuliga <[email protected]>
---
drivers/dma/xilinx/xdma-regs.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/dma/xilinx/xdma-regs.h b/drivers/dma/xilinx/xdma-regs.h
index 7a169377b483..654c5e41112d 100644
--- a/drivers/dma/xilinx/xdma-regs.h
+++ b/drivers/dma/xilinx/xdma-regs.h
@@ -102,6 +102,7 @@ struct xdma_hw_desc {
#define CHAN_CTRL_IE_MAGIC_STOPPED BIT(4)
#define CHAN_CTRL_IE_IDLE_STOPPED BIT(6)
#define CHAN_CTRL_IE_READ_ERROR GENMASK(13, 9)
+#define CHAN_CTRL_IE_WRITE_ERROR GENMASK(18, 14)
#define CHAN_CTRL_IE_DESC_ERROR GENMASK(23, 19)
#define CHAN_CTRL_NON_INCR_ADDR BIT(25)
#define CHAN_CTRL_POLL_MODE_WB BIT(26)
@@ -112,6 +113,7 @@ struct xdma_hw_desc {
CHAN_CTRL_IE_DESC_ALIGN_MISMATCH | \
CHAN_CTRL_IE_MAGIC_STOPPED | \
CHAN_CTRL_IE_READ_ERROR | \
+ CHAN_CTRL_IE_WRITE_ERROR | \
CHAN_CTRL_IE_DESC_ERROR)
/* bits of the channel interrupt enable mask */
--
2.34.1