Hi,
On 11/28/23 06:20, Borislav Petkov wrote:
> On Thu, Nov 02, 2023 at 11:42:22AM +0000, Muralidhara M K wrote:
>> From: Muralidhara M K <[email protected]>
>>
>> AMD systems with Scalable MCA, each machine check error of a SMCA bank
>> type has an associated bit position in the bank's control (CTL) register.
>
> Ontop of this. It is long overdue:
>
> ---
> From: "Borislav Petkov (AMD)" <[email protected]>
> Date: Tue, 28 Nov 2023 14:37:56 +0100
>
> Add some initial RAS documentation. The expectation is for this to
> collect all the user-visible features for interacting with the RAS
> features of the kernel.
>
In general, does RAS include EDAC and MCE?
Thanks.
> Signed-off-by: Borislav Petkov (AMD) <[email protected]>
> ---
> Documentation/RAS/ras.rst | 26 ++++++++++++++++++++++++++
> Documentation/index.rst | 1 +
> 2 files changed, 27 insertions(+)
> create mode 100644 Documentation/RAS/ras.rst
>
--
~Randy
On Tue, Nov 28, 2023 at 09:04:22AM -0800, Randy Dunlap wrote:
> In general, does RAS include EDAC and MCE?
You can say that.
--
Regards/Gruss,
Boris.
https://people.kernel.org/tglx/notes-about-netiquette