2023-12-06 08:38:33

by Jianjun Wang (王建军)

Subject: [PATCH 0/2] PCI: mediatek: Allocate MSI address with dmam_alloc_coherent

These series of patches change the allocation of MSI address on MediaTek
platform, which uses 'dmam_alloc_coherent' to allocate the MSI address.

Jianjun Wang (2):
PCI: mediatek: Allocate MSI address with dmam_alloc_coherent
PCI: mediatek-gen3: Allocate MSI address with dmam_alloc_coherent

drivers/pci/controller/pcie-mediatek-gen3.c | 30 +++++++++++----------
drivers/pci/controller/pcie-mediatek.c | 29 +++++++++++++-------
2 files changed, 36 insertions(+), 23 deletions(-)

--
2.18.0

2023-12-06 08:38:41

by Jianjun Wang (王建军)

Subject: [PATCH 2/2] PCI: mediatek-gen3: Allocate MSI address with dmam_alloc_coherent

Use 'dmam_alloc_coherent' to allocate the MSI address, instead of using
static physical address.

Signed-off-by: Jianjun Wang <[email protected]>
---
drivers/pci/controller/pcie-mediatek-gen3.c | 30 +++++++++++----------
1 file changed, 16 insertions(+), 14 deletions(-)

diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c b/drivers/pci/controller/pcie-mediatek-gen3.c
index e0e27645fdf4..0b1b5c8e5288 100644
--- a/drivers/pci/controller/pcie-mediatek-gen3.c
+++ b/drivers/pci/controller/pcie-mediatek-gen3.c
@@ -108,7 +108,7 @@
*/
struct mtk_msi_set {
void __iomem *base;
- phys_addr_t msg_addr;
+ dma_addr_t msg_addr;
u32 saved_irq_state;
};

@@ -116,7 +116,6 @@ struct mtk_msi_set {
* struct mtk_gen3_pcie - PCIe port information
* @dev: pointer to PCIe device
* @base: IO mapped register base
- * @reg_base: physical register base
* @mac_reset: MAC reset control
* @phy_reset: PHY reset control
* @phy: PHY controller block
@@ -135,7 +134,6 @@ struct mtk_msi_set {
struct mtk_gen3_pcie {
struct device *dev;
void __iomem *base;
- phys_addr_t reg_base;
struct reset_control *mac_reset;
struct reset_control *phy_reset;
struct phy *phy;
@@ -278,18 +276,24 @@ static int mtk_pcie_set_trans_table(struct mtk_gen3_pcie *pcie,
return 0;
}

-static void mtk_pcie_enable_msi(struct mtk_gen3_pcie *pcie)
+static int mtk_pcie_enable_msi(struct mtk_gen3_pcie *pcie)
{
int i;
u32 val;
+ void *msi_vaddr;

for (i = 0; i < PCIE_MSI_SET_NUM; i++) {
struct mtk_msi_set *msi_set = &pcie->msi_sets[i];

msi_set->base = pcie->base + PCIE_MSI_SET_BASE_REG +
i * PCIE_MSI_SET_OFFSET;
- msi_set->msg_addr = pcie->reg_base + PCIE_MSI_SET_BASE_REG +
- i * PCIE_MSI_SET_OFFSET;
+
+ msi_vaddr = dmam_alloc_coherent(pcie->dev, sizeof(dma_addr_t), &msi_set->msg_addr,
+ GFP_KERNEL);
+ if (!msi_vaddr) {
+ dev_err(pcie->dev, "failed to alloc and map MSI data for set %d\n", i);
+ return -ENOMEM;
+ }

/* Configure the MSI capture address */
writel_relaxed(lower_32_bits(msi_set->msg_addr), msi_set->base);
@@ -305,6 +309,8 @@ static void mtk_pcie_enable_msi(struct mtk_gen3_pcie *pcie)
val = readl_relaxed(pcie->base + PCIE_INT_ENABLE_REG);
val |= PCIE_MSI_ENABLE;
writel_relaxed(val, pcie->base + PCIE_INT_ENABLE_REG);
+
+ return 0;
}

static int mtk_pcie_startup_port(struct mtk_gen3_pcie *pcie)
@@ -371,7 +377,9 @@ static int mtk_pcie_startup_port(struct mtk_gen3_pcie *pcie)
return err;
}

- mtk_pcie_enable_msi(pcie);
+ err = mtk_pcie_enable_msi(pcie);
+ if (err)
+ return err;

/* Set PCIe translation windows */
resource_list_for_each_entry(entry, &host->windows) {
@@ -762,20 +770,14 @@ static int mtk_pcie_parse_port(struct mtk_gen3_pcie *pcie)
{
struct device *dev = pcie->dev;
struct platform_device *pdev = to_platform_device(dev);
- struct resource *regs;
int ret;

- regs = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pcie-mac");
- if (!regs)
- return -EINVAL;
- pcie->base = devm_ioremap_resource(dev, regs);
+ pcie->base = devm_platform_ioremap_resource_byname(pdev, "pcie-mac");
if (IS_ERR(pcie->base)) {
dev_err(dev, "failed to map register base\n");
return PTR_ERR(pcie->base);
}

- pcie->reg_base = regs->start;
-
pcie->phy_reset = devm_reset_control_get_optional_exclusive(dev, "phy");
if (IS_ERR(pcie->phy_reset)) {
ret = PTR_ERR(pcie->phy_reset);
--
2.18.0