The PCIe controller on SDX55 has five entries in its iommu-map, MSM8998
has one and SDM845 has sixteen, so allow wider number of items to fix
dtbs_check warnings like:
qcom-sdx55-mtp.dtb: pcie@1c00000: iommu-map: [[0, 21, 512, 1], [256, 21, 513, 1],
[512, 21, 514, 1], [768, 21, 515, 1], [1024, 21, 516, 1]] is too long
Reviewed-by: Manivannan Sadhasivam <[email protected]>
Acked-by: Conor Dooley <[email protected]>
Signed-off-by: Krzysztof Kozlowski <[email protected]>
---
Please take the patch via PCI tree.
Changes in v3:
1. None
Changes in v2:
1. Add Acs/Rb.
---
Documentation/devicetree/bindings/pci/qcom,pcie.yaml | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
index 9dbc07dfd48f..5056da499f04 100644
--- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
+++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
@@ -66,7 +66,8 @@ properties:
maxItems: 8
iommu-map:
- maxItems: 2
+ minItems: 1
+ maxItems: 16
# Common definitions for clocks, clock-names and reset.
# Platform constraints are described later.
--
2.34.1
PCI node in Qualcomm SC8180x DTS has 8 clocks:
sc8180x-primus.dtb: pci@1c00000: 'oneOf' conditional failed, one must be fixed:
['pipe', 'aux', 'cfg', 'bus_master', 'bus_slave', 'slave_q2a', 'ref', 'tbu'] is too short
Signed-off-by: Krzysztof Kozlowski <[email protected]>
---
Please take the patch via PCI tree.
Changes in v3:
1. Split from sm8150 change. Due to split/changes around sm8150, drop
Mani's Rb tag.
2. Drop unneeded oneOf for clocks.
Changes in v2:
1. Add Acs/Rb.
2. Correct error message for sm8150.
---
.../devicetree/bindings/pci/qcom,pcie.yaml | 28 ++++++++++++++++++-
1 file changed, 27 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
index 5056da499f04..5214bf7a9045 100644
--- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
+++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
@@ -483,6 +483,33 @@ allOf:
items:
- const: pci # PCIe core reset
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,pcie-sc8180x
+ then:
+ properties:
+ clocks:
+ minItems: 8
+ maxItems: 8
+ clock-names:
+ items:
+ - const: pipe # PIPE clock
+ - const: aux # Auxiliary clock
+ - const: cfg # Configuration clock
+ - const: bus_master # Master AXI clock
+ - const: bus_slave # Slave AXI clock
+ - const: slave_q2a # Slave Q2A clock
+ - const: ref # REFERENCE clock
+ - const: tbu # PCIe TBU clock
+ resets:
+ maxItems: 1
+ reset-names:
+ items:
+ - const: pci # PCIe core reset
+
- if:
properties:
compatible:
@@ -531,7 +558,6 @@ allOf:
compatible:
contains:
enum:
- - qcom,pcie-sc8180x
- qcom,pcie-sm8150
- qcom,pcie-sm8250
then:
--
2.34.1
The PCIe nodes should get the ref clock, according to information from
Qualcomm.
Link: https://lore.kernel.org/all/20231121065440.GB3315@thinkpad/
Signed-off-by: Krzysztof Kozlowski <[email protected]>
---
Patch should go via Qcom tree, if the bindings get accepted.
Changes in v3:
1. New patch
---
arch/arm64/boot/dts/qcom/sm8150.dtsi | 12 ++++++++----
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi
index 5edc557ba04a..22ee3cd5549d 100644
--- a/arch/arm64/boot/dts/qcom/sm8150.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi
@@ -1858,14 +1858,16 @@ pcie0: pci@1c00000 {
<&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
<&gcc GCC_PCIE_0_SLV_AXI_CLK>,
<&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
- <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>;
+ <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
+ <&rpmhcc RPMH_CXO_CLK>;
clock-names = "pipe",
"aux",
"cfg",
"bus_master",
"bus_slave",
"slave_q2a",
- "tbu";
+ "tbu",
+ "ref";
iommu-map = <0x0 &apps_smmu 0x1d80 0x1>,
<0x100 &apps_smmu 0x1d81 0x1>;
@@ -1949,14 +1951,16 @@ pcie1: pci@1c08000 {
<&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
<&gcc GCC_PCIE_1_SLV_AXI_CLK>,
<&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
- <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>;
+ <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
+ <&rpmhcc RPMH_CXO_CLK>;
clock-names = "pipe",
"aux",
"cfg",
"bus_master",
"bus_slave",
"slave_q2a",
- "tbu";
+ "tbu",
+ "ref";
assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
assigned-clock-rates = <19200000>;
--
2.34.1
PCI node in Qualcomm SM8150 should have exactly 8 clocks, including the
ref clock.
Suggested-by: Manivannan Sadhasivam <[email protected]>
Signed-off-by: Krzysztof Kozlowski <[email protected]>
---
Please take the patch via PCI tree.
Changes in v3:
1. New patch: Split from sc8180x change.
2. Add refclk as explained here:
https://lore.kernel.org/all/20231121065440.GB3315@thinkpad/
---
.../devicetree/bindings/pci/qcom,pcie.yaml | 26 +++++++++++++++++++
1 file changed, 26 insertions(+)
diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
index 5214bf7a9045..a93ab3b54066 100644
--- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
+++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
@@ -559,6 +559,32 @@ allOf:
contains:
enum:
- qcom,pcie-sm8150
+ then:
+ properties:
+ clocks:
+ minItems: 8
+ maxItems: 8
+ clock-names:
+ items:
+ - const: pipe # PIPE clock
+ - const: aux # Auxiliary clock
+ - const: cfg # Configuration clock
+ - const: bus_master # Master AXI clock
+ - const: bus_slave # Slave AXI clock
+ - const: slave_q2a # Slave Q2A clock
+ - const: tbu # PCIe TBU clock
+ - const: ref # REFERENCE clock
+ resets:
+ maxItems: 1
+ reset-names:
+ items:
+ - const: pci # PCIe core reset
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
- qcom,pcie-sm8250
then:
oneOf:
--
2.34.1
On Fri, 8 Dec 2023 at 12:52, Krzysztof Kozlowski
<[email protected]> wrote:
>
> PCI node in Qualcomm SM8150 should have exactly 8 clocks, including the
> ref clock.
>
> Suggested-by: Manivannan Sadhasivam <[email protected]>
> Signed-off-by: Krzysztof Kozlowski <[email protected]>
>
> ---
>
> Please take the patch via PCI tree.
>
> Changes in v3:
> 1. New patch: Split from sc8180x change.
> 2. Add refclk as explained here:
> https://lore.kernel.org/all/20231121065440.GB3315@thinkpad/
> ---
> .../devicetree/bindings/pci/qcom,pcie.yaml | 26 +++++++++++++++++++
> 1 file changed, 26 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
> index 5214bf7a9045..a93ab3b54066 100644
> --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
> +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
> @@ -559,6 +559,32 @@ allOf:
> contains:
> enum:
> - qcom,pcie-sm8150
> + then:
> + properties:
> + clocks:
> + minItems: 8
> + maxItems: 8
> + clock-names:
> + items:
> + - const: pipe # PIPE clock
> + - const: aux # Auxiliary clock
> + - const: cfg # Configuration clock
> + - const: bus_master # Master AXI clock
> + - const: bus_slave # Slave AXI clock
> + - const: slave_q2a # Slave Q2A clock
> + - const: tbu # PCIe TBU clock
> + - const: ref # REFERENCE clock
Can we change the order of the tbu and ref clocks and fold this into
the sc810x case?
> + resets:
> + maxItems: 1
> + reset-names:
> + items:
> + - const: pci # PCIe core reset
> +
> + - if:
> + properties:
> + compatible:
> + contains:
> + enum:
> - qcom,pcie-sm8250
> then:
> oneOf:
> --
> 2.34.1
>
>
--
With best wishes
Dmitry
On 08/12/2023 12:09, Dmitry Baryshkov wrote:
> On Fri, 8 Dec 2023 at 12:52, Krzysztof Kozlowski
> <[email protected]> wrote:
>>
>> PCI node in Qualcomm SM8150 should have exactly 8 clocks, including the
>> ref clock.
>>
>> Suggested-by: Manivannan Sadhasivam <[email protected]>
>> Signed-off-by: Krzysztof Kozlowski <[email protected]>
>>
>> ---
>>
>> Please take the patch via PCI tree.
>>
>> Changes in v3:
>> 1. New patch: Split from sc8180x change.
>> 2. Add refclk as explained here:
>> https://lore.kernel.org/all/20231121065440.GB3315@thinkpad/
>> ---
>> .../devicetree/bindings/pci/qcom,pcie.yaml | 26 +++++++++++++++++++
>> 1 file changed, 26 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
>> index 5214bf7a9045..a93ab3b54066 100644
>> --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
>> +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
>> @@ -559,6 +559,32 @@ allOf:
>> contains:
>> enum:
>> - qcom,pcie-sm8150
>> + then:
>> + properties:
>> + clocks:
>> + minItems: 8
>> + maxItems: 8
>> + clock-names:
>> + items:
>> + - const: pipe # PIPE clock
>> + - const: aux # Auxiliary clock
>> + - const: cfg # Configuration clock
>> + - const: bus_master # Master AXI clock
>> + - const: bus_slave # Slave AXI clock
>> + - const: slave_q2a # Slave Q2A clock
>> + - const: tbu # PCIe TBU clock
>> + - const: ref # REFERENCE clock
>
> Can we change the order of the tbu and ref clocks and fold this into
> the sc810x case?
I prefer not, because this is an ABI-concern and we are supposed to keep
things stable.
Best regards,
Krzysztof
On Fri, 8 Dec 2023 at 14:18, Krzysztof Kozlowski
<[email protected]> wrote:
>
> On 08/12/2023 12:09, Dmitry Baryshkov wrote:
> > On Fri, 8 Dec 2023 at 12:52, Krzysztof Kozlowski
> > <[email protected]> wrote:
> >>
> >> PCI node in Qualcomm SM8150 should have exactly 8 clocks, including the
> >> ref clock.
> >>
> >> Suggested-by: Manivannan Sadhasivam <[email protected]>
> >> Signed-off-by: Krzysztof Kozlowski <[email protected]>
> >>
> >> ---
> >>
> >> Please take the patch via PCI tree.
> >>
> >> Changes in v3:
> >> 1. New patch: Split from sc8180x change.
> >> 2. Add refclk as explained here:
> >> https://lore.kernel.org/all/20231121065440.GB3315@thinkpad/
> >> ---
> >> .../devicetree/bindings/pci/qcom,pcie.yaml | 26 +++++++++++++++++++
> >> 1 file changed, 26 insertions(+)
> >>
> >> diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
> >> index 5214bf7a9045..a93ab3b54066 100644
> >> --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
> >> +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
> >> @@ -559,6 +559,32 @@ allOf:
> >> contains:
> >> enum:
> >> - qcom,pcie-sm8150
> >> + then:
> >> + properties:
> >> + clocks:
> >> + minItems: 8
> >> + maxItems: 8
> >> + clock-names:
> >> + items:
> >> + - const: pipe # PIPE clock
> >> + - const: aux # Auxiliary clock
> >> + - const: cfg # Configuration clock
> >> + - const: bus_master # Master AXI clock
> >> + - const: bus_slave # Slave AXI clock
> >> + - const: slave_q2a # Slave Q2A clock
> >> + - const: tbu # PCIe TBU clock
> >> + - const: ref # REFERENCE clock
> >
> > Can we change the order of the tbu and ref clocks and fold this into
> > the sc810x case?
>
> I prefer not, because this is an ABI-concern and we are supposed to keep
> things stable.
Ack, fair enough.
--
With best wishes
Dmitry
On Fri, 08 Dec 2023 11:51:53 +0100, Krzysztof Kozlowski wrote:
> PCI node in Qualcomm SC8180x DTS has 8 clocks:
>
> sc8180x-primus.dtb: pci@1c00000: 'oneOf' conditional failed, one must be fixed:
> ['pipe', 'aux', 'cfg', 'bus_master', 'bus_slave', 'slave_q2a', 'ref', 'tbu'] is too short
>
> Signed-off-by: Krzysztof Kozlowski <[email protected]>
>
> ---
>
> Please take the patch via PCI tree.
>
> Changes in v3:
> 1. Split from sm8150 change. Due to split/changes around sm8150, drop
> Mani's Rb tag.
> 2. Drop unneeded oneOf for clocks.
>
> Changes in v2:
> 1. Add Acs/Rb.
> 2. Correct error message for sm8150.
> ---
> .../devicetree/bindings/pci/qcom,pcie.yaml | 28 ++++++++++++++++++-
> 1 file changed, 27 insertions(+), 1 deletion(-)
>
Acked-by: Rob Herring <[email protected]>
On Fri, 08 Dec 2023 11:51:54 +0100, Krzysztof Kozlowski wrote:
> PCI node in Qualcomm SM8150 should have exactly 8 clocks, including the
> ref clock.
>
> Suggested-by: Manivannan Sadhasivam <[email protected]>
> Signed-off-by: Krzysztof Kozlowski <[email protected]>
>
> ---
>
> Please take the patch via PCI tree.
>
> Changes in v3:
> 1. New patch: Split from sc8180x change.
> 2. Add refclk as explained here:
> https://lore.kernel.org/all/20231121065440.GB3315@thinkpad/
> ---
> .../devicetree/bindings/pci/qcom,pcie.yaml | 26 +++++++++++++++++++
> 1 file changed, 26 insertions(+)
>
Acked-by: Rob Herring <[email protected]>
On 8.12.2023 11:51, Krzysztof Kozlowski wrote:
> PCI node in Qualcomm SC8180x DTS has 8 clocks:
>
> sc8180x-primus.dtb: pci@1c00000: 'oneOf' conditional failed, one must be fixed:
> ['pipe', 'aux', 'cfg', 'bus_master', 'bus_slave', 'slave_q2a', 'ref', 'tbu'] is too short
>
> Signed-off-by: Krzysztof Kozlowski <[email protected]>
>
> ---
[...]
> + items:
> + - const: pipe # PIPE clock
> + - const: aux # Auxiliary clock
> + - const: cfg # Configuration clock
> + - const: bus_master # Master AXI clock
> + - const: bus_slave # Slave AXI clock
> + - const: slave_q2a # Slave Q2A clock
> + - const: ref # REFERENCE clock
> + - const: tbu # PCIe TBU clock
Are we sure this one is actually necessary? Or is it just for the
SMMU debug peripheral? [1] Would be nice to test if it works
normally (unused clk shutdown / forced shutdown of this one might
be necessary in case it's on from XBL) and during a PCIe-related
SMMU fault.
Konrad
[1] https://lore.kernel.org/linux-arm-msm/[email protected]/
On 09/12/2023 18:38, Konrad Dybcio wrote:
> On 8.12.2023 11:51, Krzysztof Kozlowski wrote:
>> PCI node in Qualcomm SC8180x DTS has 8 clocks:
>>
>> sc8180x-primus.dtb: pci@1c00000: 'oneOf' conditional failed, one must be fixed:
>> ['pipe', 'aux', 'cfg', 'bus_master', 'bus_slave', 'slave_q2a', 'ref', 'tbu'] is too short
>>
>> Signed-off-by: Krzysztof Kozlowski <[email protected]>
>>
>> ---
> [...]
>
>> + items:
>> + - const: pipe # PIPE clock
>> + - const: aux # Auxiliary clock
>> + - const: cfg # Configuration clock
>> + - const: bus_master # Master AXI clock
>> + - const: bus_slave # Slave AXI clock
>> + - const: slave_q2a # Slave Q2A clock
>> + - const: ref # REFERENCE clock
>> + - const: tbu # PCIe TBU clock
> Are we sure this one is actually necessary? Or is it just for the
> SMMU debug peripheral? [1] Would be nice to test if it works
> normally (unused clk shutdown / forced shutdown of this one might
> be necessary in case it's on from XBL) and during a PCIe-related
> SMMU fault.
I did not validate whether the list is actually correct with datasheets,
but aligned it to DTS. I don't have the hardware to test.
Best regards,
Krzysztof
On 12/11/23 11:04, Krzysztof Kozlowski wrote:
> On 09/12/2023 18:38, Konrad Dybcio wrote:
>> On 8.12.2023 11:51, Krzysztof Kozlowski wrote:
>>> PCI node in Qualcomm SC8180x DTS has 8 clocks:
>>>
>>> sc8180x-primus.dtb: pci@1c00000: 'oneOf' conditional failed, one must be fixed:
>>> ['pipe', 'aux', 'cfg', 'bus_master', 'bus_slave', 'slave_q2a', 'ref', 'tbu'] is too short
>>>
>>> Signed-off-by: Krzysztof Kozlowski <[email protected]>
>>>
>>> ---
>> [...]
>>
>>> + items:
>>> + - const: pipe # PIPE clock
>>> + - const: aux # Auxiliary clock
>>> + - const: cfg # Configuration clock
>>> + - const: bus_master # Master AXI clock
>>> + - const: bus_slave # Slave AXI clock
>>> + - const: slave_q2a # Slave Q2A clock
>>> + - const: ref # REFERENCE clock
>>> + - const: tbu # PCIe TBU clock
>> Are we sure this one is actually necessary? Or is it just for the
>> SMMU debug peripheral? [1] Would be nice to test if it works
>> normally (unused clk shutdown / forced shutdown of this one might
>> be necessary in case it's on from XBL) and during a PCIe-related
>> SMMU fault.
>
> I did not validate whether the list is actually correct with datasheets,
> but aligned it to DTS. I don't have the hardware to test.
While I can't test suspend yet, the PCIe itself works fine
without these clocks. Mani, can we get rid of it?
Konrad
Hello,
Applied to dt-bindings, thank you!
[01/04] dt-bindings: PCI: qcom: Adjust iommu-map for different SoC
https://git.kernel.org/pci/pci/c/4791c44c0a98
[02/04] dt-bindings: PCI: qcom: Correct clocks for SC8180x
https://git.kernel.org/pci/pci/c/f2ab5a2455d9
[03/04] dt-bindings: PCI: qcom: Correct clocks for SM8150
https://git.kernel.org/pci/pci/c/a711253d5f70
The above will go through the PCI tree.
Krzysztof
On Fri, 08 Dec 2023 11:51:52 +0100, Krzysztof Kozlowski wrote:
> The PCIe controller on SDX55 has five entries in its iommu-map, MSM8998
> has one and SDM845 has sixteen, so allow wider number of items to fix
> dtbs_check warnings like:
>
> qcom-sdx55-mtp.dtb: pcie@1c00000: iommu-map: [[0, 21, 512, 1], [256, 21, 513, 1],
> [512, 21, 514, 1], [768, 21, 515, 1], [1024, 21, 516, 1]] is too long
>
> [...]
Applied, thanks!
[4/4] arm64: dts: qcom: sm8150: add necessary ref clock to PCIe
commit: 6de995bc46344d5a6f0c80fee526bfb5d11c3d88
Best regards,
--
Bjorn Andersson <[email protected]>