2023-12-11 05:37:39

by guanjun

Subject: [PATCH v5 0/2] Some fixes for idxd driver

From: Guanjun <[email protected]>

Hi Dave, Fenghua,
As we talked in v1 and v2, I add fixes tag in patch 0 and change some
descriptions in patch 1.

Hi Lijun,
According to your comments, I change the fix tag to commit
eb0cf33a91b4(dmaengine: idxd: move interrupt handle assignment)

Thanks,
Guanjun

Guanjun (2):
dmaengine: idxd: Protect int_handle field in hw descriptor
dmaengine: idxd: Fix incorrect descriptions for GRPCFG register

drivers/dma/idxd/registers.h | 12 +++++++-----
drivers/dma/idxd/submit.c | 14 +++++++-------
2 files changed, 14 insertions(+), 12 deletions(-)

--
2.39.3

2023-12-11 05:37:45

by guanjun

Subject: [PATCH v5 2/2] dmaengine: idxd: Fix incorrect descriptions for GRPCFG register

From: Guanjun <[email protected]>

Fix incorrect descriptions for the GRPCFG register which has three
sub-registers (GRPWQCFG, GRPENGCFG and GRPFLGCFG).
No functional changes

Signed-off-by: Guanjun <[email protected]>
Reviewed-by: Dave Jiang <[email protected]>
Reviewed-by: Fenghua Yu <[email protected]>
Acked-by: Lijun Pan <[email protected]>
---
drivers/dma/idxd/registers.h | 12 +++++++-----
1 file changed, 7 insertions(+), 5 deletions(-)

diff --git a/drivers/dma/idxd/registers.h b/drivers/dma/idxd/registers.h
index 7b54a3939ea1..315c004f58e4 100644
--- a/drivers/dma/idxd/registers.h
+++ b/drivers/dma/idxd/registers.h
@@ -440,12 +440,14 @@ union wqcfg {
/*
* This macro calculates the offset into the GRPCFG register
* idxd - struct idxd *
- * n - wq id
- * ofs - the index of the 32b dword for the config register
+ * n - group id
+ * ofs - the index of the 64b qword for the config register
*
- * The WQCFG register block is divided into groups per each wq. The n index
- * allows us to move to the register group that's for that particular wq.
- * Each register is 32bits. The ofs gives us the number of register to access.
+ * The GRPCFG register block is divided into three sub-registers, which
+ * are GRPWQCFG, GRPENGCFG and GRPFLGCFG. The n index allows us to move
+ * to the register block that contains the three sub-registers.
+ * Each register block is 64bits. And the ofs gives us the offset
+ * within the GRPWQCFG register to access.
*/
#define GRPWQCFG_OFFSET(idxd_dev, n, ofs) ((idxd_dev)->grpcfg_offset +\
(n) * GRPCFG_SIZE + sizeof(u64) * (ofs))
--
2.39.3

2023-12-11 15:04:31

by Vinod Koul

Subject: Re: [PATCH v5 0/2] Some fixes for idxd driver

On Mon, 11 Dec 2023 13:37:02 +0800, 'Guanjun' wrote:
> As we talked in v1 and v2, I add fixes tag in patch 0 and change some
> descriptions in patch 1.
>
> Hi Lijun,
> According to your comments, I change the fix tag to commit
> eb0cf33a91b4(dmaengine: idxd: move interrupt handle assignment)
>
> [...]

Applied, thanks!

[1/2] dmaengine: idxd: Protect int_handle field in hw descriptor
commit: 778dfacc903d4b1ef5b7a9726e3a36bc15913d29
[2/2] dmaengine: idxd: Fix incorrect descriptions for GRPCFG register
commit: 0c154698a0fc32957d00c6009d5389e086dc8acf

Best regards,
--
~Vinod