From: Elad Nachman <[email protected]>
Add support for CN9130 and CN9131 COM Express Type 7 CPU
module boards by Marvell.
Add device tree bindings for this board.
Define these COM Express CPU modules as dtsi, and
provide a dtsi file for a carrier board (Marvell AC5X RD
COM Express type 7 carrier board).
This Carrier board only utilizes the PCIe link, hence no
special device / driver support is provided by this dtsi file.
Finally, add dts file for the combined carrier and CPU module.
v8:
1) swap enum for const in dt bindings
v7:
1) update MAINTAINERS file to contain all marvell arm64
dts file in one line, covering all files
2) Add Documentation to carrier dtsi and combined carrier
and CPU module dts, explaining the configuration and
modes of operations of the carrier and the combined
system.
v6:
1) Add cn9130 COM Express system
2) Drop with from compatibility name of COM Express system
3) Fix indentation issues of dt bindings
v5:
1) List only carrier compatibility on carrier dtsi
2) Fix dt_bindings_check warnings using latest yamllint/dtschema
3) Fix subject lines to remove unnecessary wordings.
4) Remove dt bindings for standalone CPU modules
5) Move CN913x dt bindings to A7K dt bindings file
6) Fix dtbs_check warnings for dtb and bindings,
using latest yamllint/dtschema.
7) Move memory definition to main dts file, as memory
is socket based.
v4:
1) reorder patches - dt bindings before dts/dtsi files
2) correct description in dt bindings
3) separate dt bindings for CPU module, carrier and combination
4) make carrier board dts into dtsi, make dts for combination of
carrier and CPU module
5) correct compatibility strings and file names to use dashes
instead of underscores
v3:
1) Remove acronym which creates warnings for checkpatch.pl
2) Correct compatibility string for ac5x rd board
3) Add above compatibility string to dt bindings
4) update MAINTAINERS file with ac5 series dts files
5) remove memory property from carrier dts
6) add comment explaining that OOB RGMII ethernet port
connector and PHY are both on CPU module
v2:
1) add compatibility string for the board
2) remove unneeded hard-coded PHY LED blinking mode initialization
3) Split the CPU portion of the carrier board to
dtsi files, and define a dts file for the AC5X RD
carrier board.
Elad Nachman (3):
MAINTAINERS: add ac5 to list of maintained Marvell dts files
dt-bindings: arm64: add Marvell COM Express boards
arm64: dts: cn913x: add device trees for COM Express boards
.../bindings/arm/marvell/armada-7k-8k.yaml | 22 ++++
MAINTAINERS | 3 +-
arch/arm64/boot/dts/marvell/Makefile | 1 +
.../dts/marvell/ac5x-rd-carrier-cn9131.dts | 44 +++++++
.../boot/dts/marvell/ac5x-rd-carrier.dtsi | 34 ++++++
.../dts/marvell/cn9130-db-comexpress.dtsi | 96 ++++++++++++++++
.../dts/marvell/cn9131-db-comexpress.dtsi | 108 ++++++++++++++++++
7 files changed, 306 insertions(+), 2 deletions(-)
create mode 100644 arch/arm64/boot/dts/marvell/ac5x-rd-carrier-cn9131.dts
create mode 100644 arch/arm64/boot/dts/marvell/ac5x-rd-carrier.dtsi
create mode 100644 arch/arm64/boot/dts/marvell/cn9130-db-comexpress.dtsi
create mode 100644 arch/arm64/boot/dts/marvell/cn9131-db-comexpress.dtsi
--
2.25.1
From: Elad Nachman <[email protected]>
Add support for CN9130 and CN9131 COM Express Type 7 CPU
module boards by Marvell.
Define these COM Express CPU modules as dtsi and
provide a dtsi file for a carrier board (Marvell AC5X RD
COM Express type 7 carrier board).
This Carrier board only utilizes the PCIe link, hence no
special device / driver support is provided by this dtsi file.
Finally, provide a dts file for the com express carrier and
CPU module combination.
These COM Express boards differ from the existing CN913x DB
boards by the type of ethernet connection (RGMII),
the type of voltage regulators (not i2c expander based)
and the USB phy (not UTMI based).
Note - PHY + RGMII connector is OOB on CPU module.
CN9131 COM Express board is basically CN9130 COM Express board
with an additional CP115 I/O co-processor, which in this case
provides an additional USB host controller on the board.
Signed-off-by: Elad Nachman <[email protected]>
---
arch/arm64/boot/dts/marvell/Makefile | 1 +
.../dts/marvell/ac5x-rd-carrier-cn9131.dts | 44 +++++++
.../boot/dts/marvell/ac5x-rd-carrier.dtsi | 34 ++++++
.../dts/marvell/cn9130-db-comexpress.dtsi | 96 ++++++++++++++++
.../dts/marvell/cn9131-db-comexpress.dtsi | 108 ++++++++++++++++++
5 files changed, 283 insertions(+)
create mode 100644 arch/arm64/boot/dts/marvell/ac5x-rd-carrier-cn9131.dts
create mode 100644 arch/arm64/boot/dts/marvell/ac5x-rd-carrier.dtsi
create mode 100644 arch/arm64/boot/dts/marvell/cn9130-db-comexpress.dtsi
create mode 100644 arch/arm64/boot/dts/marvell/cn9131-db-comexpress.dtsi
diff --git a/arch/arm64/boot/dts/marvell/Makefile b/arch/arm64/boot/dts/marvell/Makefile
index 79ac09b58a89..99b8cb3c49e1 100644
--- a/arch/arm64/boot/dts/marvell/Makefile
+++ b/arch/arm64/boot/dts/marvell/Makefile
@@ -26,4 +26,5 @@ dtb-$(CONFIG_ARCH_MVEBU) += cn9132-db.dtb
dtb-$(CONFIG_ARCH_MVEBU) += cn9132-db-B.dtb
dtb-$(CONFIG_ARCH_MVEBU) += cn9130-crb-A.dtb
dtb-$(CONFIG_ARCH_MVEBU) += cn9130-crb-B.dtb
+dtb-$(CONFIG_ARCH_MVEBU) += ac5x-rd-carrier-cn9131.dtb
dtb-$(CONFIG_ARCH_MVEBU) += ac5-98dx35xx-rd.dtb
diff --git a/arch/arm64/boot/dts/marvell/ac5x-rd-carrier-cn9131.dts b/arch/arm64/boot/dts/marvell/ac5x-rd-carrier-cn9131.dts
new file mode 100644
index 000000000000..2a0b07000089
--- /dev/null
+++ b/arch/arm64/boot/dts/marvell/ac5x-rd-carrier-cn9131.dts
@@ -0,0 +1,44 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2023 Marvell International Ltd.
+ *
+ * Device tree for the AC5X RD Type 7 Com Express carrier board,
+ * Utilizing the CN913x COM Express CPU module board.
+ * This specific carrier board in this mode of operation (external)
+ * only maintains a PCIe link with the CPU module,
+ * which does not require any special DTS definitions.
+ *
+ * AC5X RD works here in external mode (switch selectable at the back of the
+ * board), and connect via an external cable a kit
+ * which would allow it to use an external CN9131 CPU COM Express module,
+ * mounted on top of an interposer kit.
+ *
+ * So in this case, once the switch is set to external mode as explained above,
+ * the AC5X RD becomes part of the carrier solution.
+ *
+ * When the board boots in the external CPU mode, the internal CPU is disabled,
+ * and only the switch portion of the SOC acts as a PCIe end-point, Hence there
+ * is no need to describe this internal (disabled CPU) in the device tree.
+ *
+ * There is no CPU booting in this mode on the carrier, only on the
+ * CN9131 COM Express CPU module.
+ * What runs the Linux is the CN9131 on the COM Express CPU module,
+ * And it accesses the switch end-point on the AC5X RD portion of the carrier
+ * via PCIe.
+ */
+
+#include "cn9131-db-comexpress.dtsi"
+#include "ac5x-rd-carrier.dtsi"
+
+/ {
+ model = "Marvell Armada AC5X RD COM EXPRESS type 7 carrier board with CN9131 CPU module";
+ compatible = "marvell,cn9131-ac5x-carrier", "marvell,rd-ac5x-carrier",
+ "marvell,cn9131-cpu-module", "marvell,cn9131",
+ "marvell,armada-ap807-quad", "marvell,armada-ap807";
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x2 0x00000000>;
+ };
+
+};
diff --git a/arch/arm64/boot/dts/marvell/ac5x-rd-carrier.dtsi b/arch/arm64/boot/dts/marvell/ac5x-rd-carrier.dtsi
new file mode 100644
index 000000000000..f98629abb58b
--- /dev/null
+++ b/arch/arm64/boot/dts/marvell/ac5x-rd-carrier.dtsi
@@ -0,0 +1,34 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2023 Marvell International Ltd.
+ *
+ * Device tree for the AC5X RD Type 7 Com Express carrier board,
+ * This specific board in external mode (see below) only maintains
+ * a PCIe link with the COM Express CPU module, which does not
+ * require any special DTS definitions.
+ *
+ * AC5X RD can either work as you would expect, as a complete standalone
+ * box using the internal CPU, or you can move the switch on the back of
+ * the box to "external" mode, and connect via an external cable a kit
+ * which would allow it to use an external CPU COM Express module,
+ * mounted on top of an interposer kit.
+ *
+ * So in this case, once the switch is set to external mode as explained above,
+ * the AC5X RD becomes part of the carrier solution.
+ * This is a development/reference solution, not a full commercial solution,
+ * hence it was designed with the flexibility to be configured in different
+ * modes of operation.
+ *
+ * When the board boots in the external CPU mode, the internal CPU is disabled,
+ * and only the switch portion of the SOC acts as a PCIe end-point, Hence there
+ * is no need to describe this internal (disabled CPU) in the device tree.
+ *
+ * There is no CPU booting in this mode on the carrier,
+ * only on the COM Express CPU module.
+ */
+
+/ {
+ model = "Marvell Armada AC5X RD COM EXPRESS type 7 carrier board";
+ compatible = "marvell,rd-ac5x-carrier";
+
+};
diff --git a/arch/arm64/boot/dts/marvell/cn9130-db-comexpress.dtsi b/arch/arm64/boot/dts/marvell/cn9130-db-comexpress.dtsi
new file mode 100644
index 000000000000..028496ebc473
--- /dev/null
+++ b/arch/arm64/boot/dts/marvell/cn9130-db-comexpress.dtsi
@@ -0,0 +1,96 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2023 Marvell International Ltd.
+ *
+ * Device tree for the CN9130-DB Com Express CPU module board.
+ */
+
+#include "cn9130-db.dtsi"
+
+/ {
+ model = "Marvell Armada CN9130-DB COM EXPRESS type 7 CPU module board";
+ compatible = "marvell,cn9130-cpu-module", "marvell,cn9130",
+ "marvell,armada-ap807-quad", "marvell,armada-ap807";
+
+};
+
+&ap0_reg_sd_vccq {
+ regulator-max-microvolt = <1800000>;
+ states = <1800000 0x1 1800000 0x0>;
+ /delete-property/ gpios;
+};
+
+&cp0_reg_usb3_vbus0 {
+ /delete-property/ gpio;
+};
+
+&cp0_reg_usb3_vbus1 {
+ /delete-property/ gpio;
+};
+
+&cp0_reg_sd_vcc {
+ status = "disabled";
+};
+
+&cp0_reg_sd_vccq {
+ status = "disabled";
+};
+
+&cp0_sdhci0 {
+ status = "disabled";
+};
+
+&cp0_eth0 {
+ status = "disabled";
+};
+
+&cp0_eth1 {
+ status = "okay";
+ phy = <&phy0>;
+ phy-mode = "rgmii-id";
+};
+
+&cp0_eth2 {
+ status = "disabled";
+};
+
+&cp0_mdio {
+ status = "okay";
+ pinctrl-0 = <&cp0_ge_mdio_pins>;
+ phy0: ethernet-phy@0 {
+ status = "okay";
+ };
+};
+
+&cp0_syscon0 {
+ cp0_pinctrl: pinctrl {
+ compatible = "marvell,cp115-standalone-pinctrl";
+
+ cp0_ge_mdio_pins: ge-mdio-pins {
+ marvell,pins = "mpp40", "mpp41";
+ marvell,function = "ge";
+ };
+ };
+};
+
+&cp0_sdhci0 {
+ status = "disabled";
+};
+
+&cp0_spi1 {
+ status = "okay";
+};
+
+&cp0_usb3_0 {
+ status = "okay";
+ usb-phy = <&cp0_usb3_0_phy0>;
+ phy-names = "usb";
+ /delete-property/ phys;
+};
+
+&cp0_usb3_1 {
+ status = "okay";
+ usb-phy = <&cp0_usb3_0_phy1>;
+ phy-names = "usb";
+ /delete-property/ phys;
+};
diff --git a/arch/arm64/boot/dts/marvell/cn9131-db-comexpress.dtsi b/arch/arm64/boot/dts/marvell/cn9131-db-comexpress.dtsi
new file mode 100644
index 000000000000..6f3914bcfd01
--- /dev/null
+++ b/arch/arm64/boot/dts/marvell/cn9131-db-comexpress.dtsi
@@ -0,0 +1,108 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2023 Marvell International Ltd.
+ *
+ * Device tree for the CN9131-DB Com Express CPU module board.
+ */
+
+#include "cn9131-db.dtsi"
+
+/ {
+ model = "Marvell Armada CN9131-DB COM EXPRESS type 7 CPU module board";
+ compatible = "marvell,cn9131-cpu-module", "marvell,cn9131", "marvell,cn9130",
+ "marvell,armada-ap807-quad", "marvell,armada-ap807";
+
+};
+
+&ap0_reg_sd_vccq {
+ regulator-max-microvolt = <1800000>;
+ states = <1800000 0x1 1800000 0x0>;
+ /delete-property/ gpios;
+};
+
+&cp0_reg_usb3_vbus0 {
+ /delete-property/ gpio;
+};
+
+&cp0_reg_usb3_vbus1 {
+ /delete-property/ gpio;
+};
+
+&cp1_reg_usb3_vbus0 {
+ /delete-property/ gpio;
+};
+
+&cp0_reg_sd_vcc {
+ status = "disabled";
+};
+
+&cp0_reg_sd_vccq {
+ status = "disabled";
+};
+
+&cp0_sdhci0 {
+ status = "disabled";
+};
+
+&cp0_eth0 {
+ status = "disabled";
+};
+
+&cp0_eth1 {
+ status = "okay";
+ phy = <&phy0>;
+ phy-mode = "rgmii-id";
+};
+
+&cp0_eth2 {
+ status = "disabled";
+};
+
+&cp0_mdio {
+ status = "okay";
+ pinctrl-0 = <&cp0_ge_mdio_pins>;
+ phy0: ethernet-phy@0 {
+ status = "okay";
+ };
+};
+
+&cp0_syscon0 {
+ cp0_pinctrl: pinctrl {
+ compatible = "marvell,cp115-standalone-pinctrl";
+
+ cp0_ge_mdio_pins: ge-mdio-pins {
+ marvell,pins = "mpp40", "mpp41";
+ marvell,function = "ge";
+ };
+ };
+};
+
+&cp0_sdhci0 {
+ status = "disabled";
+};
+
+&cp0_spi1 {
+ status = "okay";
+};
+
+&cp0_usb3_0 {
+ status = "okay";
+ usb-phy = <&cp0_usb3_0_phy0>;
+ phy-names = "usb";
+ /delete-property/ phys;
+};
+
+&cp0_usb3_1 {
+ status = "okay";
+ usb-phy = <&cp0_usb3_0_phy1>;
+ phy-names = "usb";
+ /delete-property/ phys;
+};
+
+&cp1_usb3_1 {
+ status = "okay";
+ usb-phy = <&cp1_usb3_0_phy0>;
+ /* Generic PHY, providing serdes lanes */
+ phys = <&cp1_comphy3 1>;
+ phy-names = "usb";
+};
--
2.25.1
From: Elad Nachman <[email protected]>
Add dt bindings for:
CN9130 COM Express CPU module
CN9131 COM Express CPU module
AC5X RD COM Express Type 7 carrier board.
AC5X RD COM Express board with a CN9131 COM Express Type 7 CPU module.
Signed-off-by: Elad Nachman <[email protected]>
---
.../bindings/arm/marvell/armada-7k-8k.yaml | 22 +++++++++++++++++++
1 file changed, 22 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/marvell/armada-7k-8k.yaml b/Documentation/devicetree/bindings/arm/marvell/armada-7k-8k.yaml
index 52d78521e412..16d2e132d3d1 100644
--- a/Documentation/devicetree/bindings/arm/marvell/armada-7k-8k.yaml
+++ b/Documentation/devicetree/bindings/arm/marvell/armada-7k-8k.yaml
@@ -60,4 +60,26 @@ properties:
- const: marvell,armada-ap807-quad
- const: marvell,armada-ap807
+ - description:
+ Alleycat5X (98DX35xx) Reference Design as COM Express Carrier plus
+ Armada CN9130 COM Express CPU module
+ items:
+ - const: marvell,cn9130-ac5x-carrier
+ - const: marvell,rd-ac5x-carrier
+ - const: marvell,cn9130-cpu-module
+ - const: marvell,cn9130
+ - const: marvell,armada-ap807-quad
+ - const: marvell,armada-ap807
+
+ - description:
+ Alleycat5X (98DX35xx) Reference Design as COM Express Carrier plus
+ Armada CN9131 COM Express CPU module
+ items:
+ - const: marvell,cn9131-ac5x-carrier
+ - const: marvell,rd-ac5x-carrier
+ - const: marvell,cn9131-cpu-module
+ - const: marvell,cn9131
+ - const: marvell,armada-ap807-quad
+ - const: marvell,armada-ap807
+
additionalProperties: true
--
2.25.1
On Mon, Dec 11, 2023 at 07:17:38PM +0200, Elad Nachman wrote:
> From: Elad Nachman <[email protected]>
>
> Add dt bindings for:
> CN9130 COM Express CPU module
> CN9131 COM Express CPU module
> AC5X RD COM Express Type 7 carrier board.
> AC5X RD COM Express board with a CN9131 COM Express Type 7 CPU module.
>
> Signed-off-by: Elad Nachman <[email protected]>
Acked-by: Conor Dooley <[email protected]>
Cheers,
Conor.
> ---
> .../bindings/arm/marvell/armada-7k-8k.yaml | 22 +++++++++++++++++++
> 1 file changed, 22 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/arm/marvell/armada-7k-8k.yaml b/Documentation/devicetree/bindings/arm/marvell/armada-7k-8k.yaml
> index 52d78521e412..16d2e132d3d1 100644
> --- a/Documentation/devicetree/bindings/arm/marvell/armada-7k-8k.yaml
> +++ b/Documentation/devicetree/bindings/arm/marvell/armada-7k-8k.yaml
> @@ -60,4 +60,26 @@ properties:
> - const: marvell,armada-ap807-quad
> - const: marvell,armada-ap807
>
> + - description:
> + Alleycat5X (98DX35xx) Reference Design as COM Express Carrier plus
> + Armada CN9130 COM Express CPU module
> + items:
> + - const: marvell,cn9130-ac5x-carrier
> + - const: marvell,rd-ac5x-carrier
> + - const: marvell,cn9130-cpu-module
> + - const: marvell,cn9130
> + - const: marvell,armada-ap807-quad
> + - const: marvell,armada-ap807
> +
> + - description:
> + Alleycat5X (98DX35xx) Reference Design as COM Express Carrier plus
> + Armada CN9131 COM Express CPU module
> + items:
> + - const: marvell,cn9131-ac5x-carrier
> + - const: marvell,rd-ac5x-carrier
> + - const: marvell,cn9131-cpu-module
> + - const: marvell,cn9131
> + - const: marvell,armada-ap807-quad
> + - const: marvell,armada-ap807
> +
> additionalProperties: true
> --
> 2.25.1
>
On Mon, Dec 11, 2023 at 07:17:38PM +0200, Elad Nachman wrote:
> From: Elad Nachman <[email protected]>
>
> Add dt bindings for:
> CN9130 COM Express CPU module
> CN9131 COM Express CPU module
> AC5X RD COM Express Type 7 carrier board.
> AC5X RD COM Express board with a CN9131 COM Express Type 7 CPU module.
>
> Signed-off-by: Elad Nachman <[email protected]>
Reviewed-by: Andrew Lunn <[email protected]>
Andrew
On Mon, Dec 11, 2023 at 07:17:39PM +0200, Elad Nachman wrote:
> From: Elad Nachman <[email protected]>
>
> Add support for CN9130 and CN9131 COM Express Type 7 CPU
> module boards by Marvell.
> Define these COM Express CPU modules as dtsi and
> provide a dtsi file for a carrier board (Marvell AC5X RD
> COM Express type 7 carrier board).
> This Carrier board only utilizes the PCIe link, hence no
> special device / driver support is provided by this dtsi file.
> Finally, provide a dts file for the com express carrier and
> CPU module combination.
>
> These COM Express boards differ from the existing CN913x DB
> boards by the type of ethernet connection (RGMII),
> the type of voltage regulators (not i2c expander based)
> and the USB phy (not UTMI based).
> Note - PHY + RGMII connector is OOB on CPU module.
> CN9131 COM Express board is basically CN9130 COM Express board
> with an additional CP115 I/O co-processor, which in this case
> provides an additional USB host controller on the board.
>
> Signed-off-by: Elad Nachman <[email protected]>
Reviewed-by: Andrew Lunn <[email protected]>
Andrew
Elad Nachman <[email protected]> writes:
> From: Elad Nachman <[email protected]>
>
> Add support for CN9130 and CN9131 COM Express Type 7 CPU
> module boards by Marvell.
> Add device tree bindings for this board.
> Define these COM Express CPU modules as dtsi, and
> provide a dtsi file for a carrier board (Marvell AC5X RD
> COM Express type 7 carrier board).
> This Carrier board only utilizes the PCIe link, hence no
> special device / driver support is provided by this dtsi file.
> Finally, add dts file for the combined carrier and CPU module.
>
> v8:
> 1) swap enum for const in dt bindings
>
> v7:
> 1) update MAINTAINERS file to contain all marvell arm64
> dts file in one line, covering all files
> 2) Add Documentation to carrier dtsi and combined carrier
> and CPU module dts, explaining the configuration and
> modes of operations of the carrier and the combined
> system.
>
> v6:
> 1) Add cn9130 COM Express system
>
> 2) Drop with from compatibility name of COM Express system
>
> 3) Fix indentation issues of dt bindings
>
> v5:
>
> 1) List only carrier compatibility on carrier dtsi
>
> 2) Fix dt_bindings_check warnings using latest yamllint/dtschema
>
> 3) Fix subject lines to remove unnecessary wordings.
>
> 4) Remove dt bindings for standalone CPU modules
>
> 5) Move CN913x dt bindings to A7K dt bindings file
>
> 6) Fix dtbs_check warnings for dtb and bindings,
> using latest yamllint/dtschema.
>
> 7) Move memory definition to main dts file, as memory
> is socket based.
>
> v4:
> 1) reorder patches - dt bindings before dts/dtsi files
>
> 2) correct description in dt bindings
>
> 3) separate dt bindings for CPU module, carrier and combination
>
> 4) make carrier board dts into dtsi, make dts for combination of
> carrier and CPU module
>
> 5) correct compatibility strings and file names to use dashes
> instead of underscores
>
> v3:
> 1) Remove acronym which creates warnings for checkpatch.pl
>
> 2) Correct compatibility string for ac5x rd board
>
> 3) Add above compatibility string to dt bindings
>
> 4) update MAINTAINERS file with ac5 series dts files
>
> 5) remove memory property from carrier dts
>
> 6) add comment explaining that OOB RGMII ethernet port
> connector and PHY are both on CPU module
>
> v2:
> 1) add compatibility string for the board
>
> 2) remove unneeded hard-coded PHY LED blinking mode initialization
>
> 3) Split the CPU portion of the carrier board to
> dtsi files, and define a dts file for the AC5X RD
> carrier board.
>
> Elad Nachman (3):
> MAINTAINERS: add ac5 to list of maintained Marvell dts files
> dt-bindings: arm64: add Marvell COM Express boards
> arm64: dts: cn913x: add device trees for COM Express boards
Applied on mvebu/dt64
Thanks,
Gregory
>
> .../bindings/arm/marvell/armada-7k-8k.yaml | 22 ++++
> MAINTAINERS | 3 +-
> arch/arm64/boot/dts/marvell/Makefile | 1 +
> .../dts/marvell/ac5x-rd-carrier-cn9131.dts | 44 +++++++
> .../boot/dts/marvell/ac5x-rd-carrier.dtsi | 34 ++++++
> .../dts/marvell/cn9130-db-comexpress.dtsi | 96 ++++++++++++++++
> .../dts/marvell/cn9131-db-comexpress.dtsi | 108 ++++++++++++++++++
> 7 files changed, 306 insertions(+), 2 deletions(-)
> create mode 100644 arch/arm64/boot/dts/marvell/ac5x-rd-carrier-cn9131.dts
> create mode 100644 arch/arm64/boot/dts/marvell/ac5x-rd-carrier.dtsi
> create mode 100644 arch/arm64/boot/dts/marvell/cn9130-db-comexpress.dtsi
> create mode 100644 arch/arm64/boot/dts/marvell/cn9131-db-comexpress.dtsi
>
> --
> 2.25.1
>
--
Gregory Clement, Bootlin
Embedded Linux and Kernel engineering
http://bootlin.com