Hi,
Depends on:
https://lore.kernel.org/all/[email protected]/
Bindings were already applied.
Best regards,
Krzysztof
Cc: Abel Vesa <[email protected]>
Krzysztof Kozlowski (2):
arm64: dts: qcom: x1e80100: add ADSP GPR
arm64: dts: qcom: x1e80100: add LPASS LPI pin controller
arch/arm64/boot/dts/qcom/x1e80100.dtsi | 56 ++++++++++++++++++++++++++
1 file changed, 56 insertions(+)
--
2.34.1
Add the ADSP Generic Packet Router (GPR) device node as part of audio
subsystem in Qualcomm X1E80100 SoC.
Cc: Abel Vesa <[email protected]>
Signed-off-by: Krzysztof Kozlowski <[email protected]>
---
arch/arm64/boot/dts/qcom/x1e80100.dtsi | 41 ++++++++++++++++++++++++++
1 file changed, 41 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
index 61cc36554eab..aee3dbe753b1 100644
--- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi
+++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
@@ -16,6 +16,7 @@
#include <dt-bindings/phy/phy-qcom-qmp.h>
#include <dt-bindings/power/qcom,rpmhpd.h>
#include <dt-bindings/power/qcom-rpmpd.h>
+#include <dt-bindings/soc/qcom,gpr.h>
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
/ {
@@ -4741,6 +4742,46 @@ IPCC_MPROC_SIGNAL_GLINK_QMP
label = "lpass";
qcom,remote-pid = <2>;
+
+ gpr {
+ compatible = "qcom,gpr";
+ qcom,glink-channels = "adsp_apps";
+ qcom,domain = <GPR_DOMAIN_ID_ADSP>;
+ qcom,intents = <512 20>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ q6apm: service@1 {
+ compatible = "qcom,q6apm";
+ reg = <GPR_APM_MODULE_IID>;
+ #sound-dai-cells = <0>;
+ qcom,protection-domain = "avs/audio",
+ "msm/adsp/audio_pd";
+
+ q6apmbedai: bedais {
+ compatible = "qcom,q6apm-lpass-dais";
+ #sound-dai-cells = <1>;
+ };
+
+ q6apmdai: dais {
+ compatible = "qcom,q6apm-dais";
+ iommus = <&apps_smmu 0x1001 0x80>,
+ <&apps_smmu 0x1061 0x0>;
+ };
+ };
+
+ q6prm: service@2 {
+ compatible = "qcom,q6prm";
+ reg = <GPR_PRM_MODULE_IID>;
+ qcom,protection-domain = "avs/audio",
+ "msm/adsp/audio_pd";
+
+ q6prmcc: clock-controller {
+ compatible = "qcom,q6prm-lpass-clocks";
+ #clock-cells = <2>;
+ };
+ };
+ };
};
};
--
2.34.1
Add the Low Power Audio SubSystem Low Power Island (LPASS LPI) pin
controller device node as part of audio subsystem in Qualcomm X1E80100
SoC.
Cc: Abel Vesa <[email protected]>
Signed-off-by: Krzysztof Kozlowski <[email protected]>
---
arch/arm64/boot/dts/qcom/x1e80100.dtsi | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
index aee3dbe753b1..8c18d7f82166 100644
--- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi
+++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
@@ -18,6 +18,7 @@
#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/soc/qcom,gpr.h>
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
+#include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h>
/ {
interrupt-parent = <&intc>;
@@ -2980,6 +2981,20 @@ nsp_noc: interconnect@320c0000 {
#interconnect-cells = <2>;
};
+ lpass_tlmm: pinctrl@6e80000 {
+ compatible = "qcom,x1e80100-lpass-lpi-pinctrl", "qcom,sm8550-lpass-lpi-pinctrl";
+ reg = <0 0x06e80000 0 0x20000>,
+ <0 0x07250000 0 0x10000>;
+
+ clocks = <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+ <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
+ clock-names = "core", "audio";
+
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&lpass_tlmm 0 0 23>;
+ };
+
lpass_ag_noc: interconnect@7e40000 {
compatible = "qcom,x1e80100-lpass-ag-noc";
reg = <0 0x7e40000 0 0xE080>;
--
2.34.1
On 12/12/23 13:56, Krzysztof Kozlowski wrote:
> Add the Low Power Audio SubSystem Low Power Island (LPASS LPI) pin
> controller device node as part of audio subsystem in Qualcomm X1E80100
> SoC.
>
> Cc: Abel Vesa <[email protected]>
> Signed-off-by: Krzysztof Kozlowski <[email protected]>
> ---
Reviewed-by: Konrad Dybcio <[email protected]>
Konrad
On Tue, 12 Dec 2023 13:56:30 +0100, Krzysztof Kozlowski wrote:
> Depends on:
> https://lore.kernel.org/all/[email protected]/
>
> Bindings were already applied.
>
> Best regards,
> Krzysztof
>
> [...]
Applied, thanks!
[1/2] arm64: dts: qcom: x1e80100: add ADSP GPR
commit: 99f63aea9149e09239872a7315415f2d4be8ac86
[2/2] arm64: dts: qcom: x1e80100: add LPASS LPI pin controller
commit: 060df4cbfe111d9034866f9e9757d191a22719fe
Best regards,
--
Bjorn Andersson <[email protected]>